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Introduction
•
identifying code as cacheable or non-cacheable
•
selecting between the mini-data cache or data cache
•
write-back or write-through data caching
•
enabling data write allocation policy
•
enabling the write buffer to coalesce stores to external memory
Refer to
Chapter 3, "Memory Management"
1.2.2.3
Instruction Cache
The Intel® XScale™ core implements a 32-Kbyte, 32-way set associative instruction cache with a
line size of 32 bytes. All requests that "miss" the instruction cache generate a 32-byte read request
to external memory. A mechanism to lock critical code within the cache is also provided.
Refer to
Chapter 4, "Instruction Cache"
In addition to the main instruction cache there is a 2-Kbyte mini-instruction cache dedicated to
advanced debugging features. Refer to
1.2.2.4
Branch Target Buffer
The Intel® XScale™ core provides a Branch Target Buffer (BTB) to predict the outcome of branch
type instructions. It provides storage for the target address of branch type instructions and predicts
the next address to present to the instruction cache when the current instruction address is that of a
branch.
The BTB holds 128 entries. Refer to
1.2.2.5
Data Cache
The Intel® XScale™ core implements a 32-Kbyte, 32-way set associative data cache and a 2-
Kbyte, 2-way set associative mini-data cache. Each cache has a line size of 32 bytes, supporting
write-through or write-back caching.
The data/mini-data cache is controlled by page attributes defined in the MMU Architecture and by
coprocessor 15.
Refer to
Chapter 6, "Data Cache"
The Intel® XScale™ core allows applications to re-configure a portion of the data cache as data
RAM. Software may place special tables or frequently used variables in this RAM. Refer to
Section 6.4, "Re-configuring the Data Cache as Data RAM" on page 6-10
1.2.2.6
Fill Buffer & Write Buffer
The Fill Buffer and Write Buffer enable the loading and storing of data to memory beyond the
Intel® XScale™ core. The Write Buffer carries all write traffic beyond the core allowing data
coalescing when both globally enabled, and when associated with the appropriate memory page
types. The Fill buffer assists the loading of data from memory, which along with an associated
Pend Buffer allows multiple memory reads to be outstanding. Another key function of the Fill
1-4
for more information.
for more information.
Chapter 10, "Software Debug"
Chapter 5, "Branch Target Buffer"
for more information.
Intel® XScale™ Microarchitecture User's Manual
for more information.
for more information.
for more information.
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