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Table 7-7. Auxiliary Control Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: writable bits set to 0
Bits
31:6
5:4
3:2
1
0
7.2.3
Register 2: Translation Table Base Register
Table 7-8. Translation Table Base Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:14
13:0
Intel® XScale™ Microarchitecture User's Manual
Access
Read-Unpredictable /
Write-as-Zero
Read / Write
Read-Unpredictable /
Write-as-Zero
Read / Write
Read / Write
Translation Table Base
Access
Read / Write
Read-unpredictable / Write-as-Zero
8
Description
Reserved
Mini Data Cache Attributes (MD)
All configurations options for the Mini-data cache via
these bits apply to mini-data cacheable accesses, stores
are buffered in the write buffer and stores will coalesce in
the write buffer as long as coalescing is globally enabled
(K = 0 in this register).
0b00 = Write back, Read allocate
0b01 = Write back, Read/Write allocate
0b10 = Write through, Read allocate
0b11 = Unpredictable
Reserved
Page Table Memory Attribute (P)
the
This field is undefined in
implementation and must always be programmed as
zero.
Write Buffer Coalescing Disable (K)
This bit globally disables the coalescing of all stores in the
write buffer no matter what the value of the Cacheable
and Bufferable bits are in the page table descriptors.
0 = Coalescing Enabled as Page Descriptors
1 = Coalescing Disabled
8
Description
Translation Table Base - Physical address of the base of
the first-level descriptor table
Reserved
Configuration
7
6
5
4
3
2
1
0
MD
P K
PXA255 processor
7
6
5
4
3
2
1
0
7-7
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