Dvob And Dvoc Port Flexible (Modular) Design; Dvob And Dvoc Module Design; Figure 45. Dvo Enabled Simulation Model; Table 41. Allowable Interconnect Skew Calculation - Intel 852GME Design Manual

R

Table 41. Allowable Interconnect Skew Calculation

Component
Driver
Interconnect
Receiver
All numbers in this table are from the 852GME GMCH specification documents that are applicable for this
NOTE:
interface. For third party receiver devices, please refer to appropriate third party vendor specifications.
7.4.

DVOB and DVOC port Flexible (Modular) Design

The GMCH supports flexible design interfaces described in this section.
7.4.1.

DVOB and DVOC Module Design

The 852GME GMCH supports a DVO module design connected to the GMCH through a generic
connector. Simulation method is the same as in Section 7.3.4. Lengths L1 and L2 are determined by
simulation as L1= 4 inches and L2= 2 inches. Refer to Figure 46 for the generic connector parasitic
model.

Figure 45. DVO Enabled Simulation Model

All signals should be routed as striplines (inner layers).All signals in a signal group should be routed on
the same layer. Routing studies have shown that these guidelines can be met. The trace length and trace
spacing requirements must not be violated by any signal. Trace length mismatch for all signals within a
signal group should be as close to ± 100 mils with respect to the strobe clocks as possible to provide
optimal timing margin.
Table 42 shows DVO enabled routing guideline summary.
124
Skew Element
Data Valid before Strobe
Data Valid after Strobe
Allowable Skew
Data Setup to Strobe
Data Hold from Strobe
DVOB &
DVOC I/F
GMCH
® ®
Intel 852GME, Intel 852GMV and Intel
Integrated Graphics Display Port
Symbol Setup
tDVb 570
tDVa
TBD
tDSu TBD
tDh
L1 L2
Connector
tDVb, tDVa tDVb, tDVa,
tDSu, tDh tDSu, tDh
Generic
Connector
®
852PM Chipset Platforms Design Guide
Hold Units
ps
770 ps
TBD ps
ps
TBD ps
with
DVO
module