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A data abort due to a data/mini-data cache parity error may not be recoverable if the data address
that caused the abort occurred on a line in the cache that has a write-back caching policy. Prior
updates to this line may be lost; in this case the software exception handler should perform a "clean
and clear" operation on the data cache, ignoring subsequent parity errors, and restart the offending
process. The "clean & clear" operation is shown in
6.2.6
Atomic Accesses
The SWP and SWPB instructions generate an atomic load and store operation to a common
location, allowing a memory semaphore to be loaded and altered without interruption. These
accesses may hit or miss the data/mini-data cache depending on the configuration of the cache,
configuration of the MMU, and the page attributes.
The application processor guarantees that no other on-chip master (or process) divides a
SWPB
instruction. Note that there is no external bus lock pin, hence software coherency is
compulsory if companion chips are to be required to access semaphores in external memory.
6.3
Data Cache and Mini-Data Cache Control
6.3.1
Data Memory State After Reset
After processor reset, both the data cache and mini-data cache are disabled, all valid bits are set to
zero (invalid), and the round-robin bit points to way 31. Any lines in the data cache that were
configured as data RAM before reset are changed back to cacheable lines after reset, i.e., there are
32 KBytes of data cache and zero bytes of data RAM.
6.3.2
Enabling/Disabling
The data cache and mini-data cache are enabled by setting bit 2 in coprocessor 15, register 1
(Control Register). See
Example 6-1
enabled to use the data cache.
Example 6-1. Enabling the Data Cache
enableDCache:
Intel® XScale™ Microarchitecture User's Manual
Chapter 7,
"Configuration", for a description of this register and others.
shows code that enables the data and mini-data caches. Note that the MMU must be
MCR p15, 0, r0, c7, c10, 4; Drain pending data operations...
; (see Chapter 7.2.8, Register 7: Cache functions)
MRC p15, 0, r0, c1, c0, 0; Get current control register
ORR r0, r0, #4
; Enable D-Cache by setting 'C' (bit 2)
MCR p15, 0, r0, c1, c0, 0; And update the Control register
Section
6.3.3.1.
Data Cache
SWP
or
6-7
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