C0Wrdatactrl - Channel 0 Write Data Control; Channel 0 Write Data Control Registers - Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
6.1.5

C0WRDATACTRL - Channel 0 Write Data Control

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
Table 19.

Channel 0 Write Data Control Registers

Bit
23:16
15
14:0
® TM
Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
August 2010
Document Number: 323178-003
Default
Access
Value
RW 00h
RW 0b
RW 4110h
0/0/0/MCHBAR
24D-24Fh
004111h
RW
24 bits
00h
RST/
PWR
Core ECC bit invert vector (C0sd_cr_eccbitinv):
This vector operates individually for every ECC
bit in the selected 64b ECC block, during write
to DRAM. For all k between 0 and 7, when
bit(k) is set to 1, the value for the k ECC bit
(which corresponds with k data byte lane) is
inverted. Otherwise, the value for the k ECC bit
is not affected.
Core ECC Diagnostic Enable
(C0sd_cr_eccdiagen):
1: The ECC bit invert vector is used to invert
selected ECC bits, during writes to DRAM.
0: The diagnostic feature is turned off.
Core Reserved
® ®
Celeron Processor P4505, U3405 Series
Description
Datasheet Addendum
77