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Table 46. Hub Interface Signals External Layer Routing Summary
Signal
HI_[7:0]
HI_STB
and
HI_STB#
8.3.
Hub Interface Data HI[10:8] Signals
The maximum length for the hub interface data signals, HI[10:8] is 8 inches. They should be routed on
the same layer with Hl[7:0].
8.3.1.
Internal Layer Routing
Traces should be routed 4 mils wide with 8 mils trace spacing (4 on 8) and 20 mils spacing from other
non-hub interface related signals. In order to break out of the Intel 855PM MCH and Intel 82801DBM
ICH4-M packages, the HI[10:8] signals can be routed 4 on 4. The signal must be separated to 4 on 8
within 300 mils from the package.
8.3.2.
External Layer Routing
Traces should be routed 5 mils wide with 10 mils trace spacing (5 on 10) and 20 mils spacing from other
non-hub interface signals. In order to break out of the Intel 855PM MCH and Intel 82801DBM ICH4-M
packages, the HI[10:8] signals can be routed 5 on 5. The signal must be separated to 4 on 8 within 300
mils from the package.
8.3.3.
Terminating HI[11]
The HI[11] signal exists on the Intel 82801DBM ICH4-M but not the Intel 855PM MCH and is not used
on the platform. It can be left as a no connect.
8.4.
HIREF/HI_VSWING Generation/Distribution
HIREF is the hub interface reference voltage used on both the Intel 855PM MCH and the Intel
82801DBM ICH4-M. Depending on the buffer mode, the HIREF voltage requirement must be set
appropriately for proper operation. The ICH4-M uses HI_VSWING to control voltage swing and
impedance strength of the hub interface buffers. See the table below for the HIREF and HI_VSWING
voltage specifications and the associated resistor recommendations for the voltage divider circuit.
®
Intel
855PM Chipset Platform Design Guide
Max
Width
Space
length
(mils)
(mils)
(inch)
6
5
10
6
5
10
Mismatch
Relative To
length
(mils)
± 100
Differential
HI_STB pair
± 100
Data lines
Hub Interface
Space with
Notes
other signals
(mils)
20
20
HI_STB and
HI_STB# must
be the same
length (± 10
mils)
179
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