Gbe Rgmii Transmit Path Data\Control Topology - Intel EP80579 Manual

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Intel EP80579 Integrated Processor Product Line—Gigabit Ethernet (GbE) Interface
Figure 139. GbE RGMII Transmit Path Data\Control Topology
RGMII Transmit Path Data\Control Topology
(EP80579 PHY)
L
Pull_up
V2P5
Rpull_up
Pull_Up
TL (μs)
PHY
EP80579
Break out Board Break in
Via
Via
Transmitter Receiver
(Data\Ctrl)
(Data\Ctrl)
LD\C_Brk_out_tx LD\C_Brd_route_tx LD\C_Brk_in_tx
L
L
L L
D\C_Brk_in_tx
D\C_Total_tx = D\C_Brk_out_tx + D\C_Brd_route_tx +
NOTE: Breakout\ Breakin descriptions are as follows:
1. Routing where trace is 3.75 mil wide and 4mil spacing is implemented to escape\ enter BGA
2. The Breakout \ Breakin Length is defined from the pin of the BGA, to where 4 mil spacing
increases to the required spacing per SI recommendations.
a). Data\Ctrl = 12 mil edge-to-edge (e2e) for Stripline
b). Data\Ctrl = 18 mil edge-to-edge (e2e) for Microstrip
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
221 Order Number: 320068-005US