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Run–
Test/Idle
Select–
DR–Scan
Capture–DR
Exit1–DR
Figure 6-2. TAP Controller Finite State Machine
Following is a brief description of each of the states of the TAP controller state machine.
Refer to the IEEE 1149.1 standard for detailed descriptions of the states and their operation.
•
Test-Logic-Reset: In this state, the test logic is disabled so that normal operation of the
processor can continue. In this state, the instruction in the Instruction Register is forced
to IDCODE. The controller is guaranteed to enter Test-Logic-Reset when the TMS input
is held active for at least five clocks. The controller also enters this state immediately
when TRST# is pulled active, and automatically upon power-up of the processor. The
TAP controller cannot leave this state as long as TRST# is held active.
•
Run-Test/Idle: This is the idle state of the TAP controller. In this state, the contents of
all test data registers retain their previous values.
•
Select-IR-Scan: This is a temporary controller state. All registers retain their previous
values.
•
Capture-IR: In this state, the shift register contained in the Instruction Register loads a
fixed value (of which the two least significant bits are "01") on the rising edge of TCK.
The parallel, latched output of the Instruction Register ("current instruction") does not
change.
•
Shift-IR: The shift register contained in the Instruction Register is connected between
TDI and TDO and is shifted one stage toward its serial output on each rising edge of
TCK. The output arrives at TDO on the falling edge of TCK. The current instruction
does not change.
•
Exit1-IR: This is a temporary state. The current instruction does not change.
Shift–DR
Pause–DR
Exit2–DR
Update–DR
TEST ACCESS PORT (TAP)
Test–
Logic Reset
Select–
IR–Scan
Capture–DR
Shift–DR
Exit1–DR
Pause–DR
Update–DR
TMS 1
TMS 0
Exit2–DR
000941
6-3
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