Table of Contents
Advertisement
PENTIUM® PRO PROCESSOR TEST ACCESS PORT (TAP)
10.1.
INTERFACE
The TAP logic is accessed serially through 5 dedicated pins on the Pentium Pro processor
package:
TCK: The TAP clock signal
•
TMS: "Test mode select," which controls the TAP finite state machine
•
TDI: "Test data input," which inputs test instructions and data serially
•
TRST#: "Test reset," for TAP logic reset
•
TDO: "Test data output," through which test output is read serially
•
TMS, TDI and TDO operate synchronously with TCK (which is independent of any other Pen-
tium Pro processor clock). TRST# is an asynchronous input signal.
10.2.
ACCESSING THE TAP LOGIC
The Pentium Pro processor TAP is accessed through a 1149.1-compliant TAP controller finite
state machine. This finite state machine, shown in Figure 10-2, contains a reset state, a run-
test/idle state, and two major branches. These branches allow access either to the TAP Instruc-
tion Register or to one of the data registers. The TMS pin is used as the controlling input to
traverse this finite state machine. TAP instructions and test data are loaded serially (in the Shift-
IR and Shift-DR states, respectively) using the TDI pin. State transitions are made on the rising
edge of TCK.
Run-Test/
Idle
Select-
DR-Scan
Capture-DR Shift-DR
Exit1-DR
Figure 10-2. TAP Controller Finite State Machine
10-2
Pause-DR
Exit2-DR
Update-DR
Test-Logic
Reset
TMS 1
TMS 0
Select -
IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Update-IR
Exit2-IR
Advertisement
Table of Contents
