Signal Descriptions; Operation; Tap Controller Reset - Intel PXA27 Series Design Manual

26.3

Signal Descriptions

The TAP interface is controlled through five dedicated pins: TDI, TMS, TCK, nTRST, and TDO.
See Table 26-1
Table 26-1. TAP Controller Pin Definitions
Signal
Name
TCK
TMS
TDI
TDO
nTRST
26.4

Operation

This section describes the operation of the JTAG interface and TAP controller implemented in the
PXA27x processor.
26.4.1

TAP Controller Reset

The boundary-scan interface includes a synchronous finite state machine, the TAP controller (see
Figure 26-3). In order to force the TAP controller into the correct state, a reset pulse must be
applied to the nTRST pin. This forces the TAP controller into the Test-Logic-Reset state (TLRS).
A clock on TCK is not necessary to reset the TAP controller.
To use the boundary-scan interface, these requirements must be met:
•
During power-up, nTRST must be driven from low to high either before or at the same time as
nRESET.
•
During power-up, 10 µs must elapse after nTRST is de-asserted before proceeding with any
JTAG operation.
•
For JTAG TAP operation, the nBATT_FAULT and nVCC_FAULT pins must always be driven
high (de-asserted). An active low signal on either pin puts the device into sleep mode, which
powers down all JTAG circuitry.
®
Intel PXA27x Processor Family Design Guide
for description of these pins.
Directio
n
Input Test Clock — clock input for the TAP controller and instruction and test data registers
Test Mode Select — controls operation of the TAP controller
Input
The TMS input is pulled high when it is not being driven. TMS is sampled on the rising
edge of TCK.
Test Data In — serial data input to the instruction and test data registers
Input
Data at TDI is sampled on the rising edge of TCK. TDI is pulled high when it is not being
driven.
Test Data Out — serial data output
Data at TDO is clocked out on the falling edge of TCK. It provides an inactive (high-
Output
impedance) state during non-shift operations to support parallel connection of TDO
outputs at the board or module level.
Test Reset — provides asynchronous initialization of the JTAG test logic
Asserting this pin puts the TAP controller in the Test-Logic-Reset state. An external
Input
source must drive nTRST before or at the same time as the hardware nRESET pin for
correct TAP controller and device operation.
Description
JTAG Debug
II:26-3