Rx Register Ready Bit (Rr) - Intel PXA255 User Manual

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Software Debug
Table 10-8. TX RX Control Register (TXRXCTRL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
O
D
R
V
reset value: 0x0000_0000
Bits
31
30
29
28
27:0
10.7.1

RX Register Ready Bit (RR)

The debugger and debug handler use the RR bit to synchronize accesses to RX. Normally, the
debugger and debug handler use a handshaking scheme that requires both sides to poll the RR bit.
To support higher download performance for large amounts of data, a high-speed download
handshaking scheme can be used in which only the debug handler polls the RR bit before accessing
the RX register, while the debugger continuously downloads data.
Table 10-9
Table 10-9. Normal RX Handshaking
Debugger Actions
Debugger wants to send data to debug handler.
Before writing new data to the RX register, the debugger polls RR through JTAG until the bit is cleared.
After the debugger reads a '0' from the RR bit, it scans data into JTAG to write to the RX register and sets the
valid bit. The write to the RX register automatically sets the RR bit.
Debug Handler Actions
Debug handler is expecting data from the debugger.
The debug handler polls the RR bit until it is set, indicating data in the RX register is valid.
Once the RR bit is set, the debug handler reads the new data from the RX register. The read operation
automatically clears the RR bit.
When data is being downloaded by the debugger, part of the normal handshaking can be bypassed
to allow the download rate to be increased.
debugger is doing a high-speed download. Before the high-speed download can start, both the
debugger and debug handler must be synchronized, such that the debug handler is executing a
routine that supports the high-speed download.
10-12
T
R
Access
Software Read-only / Write-ignored
JTAG Write-only
Software Read / Write
Software Read-only/ Write-ignored
JTAG Write-only
Software Read-only/ Write-ignored
JTAG Write-only
Read-as-Zero / Write-ignored
shows the normal handshaking used to access the RX register.
Description
RR
1=RX Register Ready
OV
1=RX overflow sticky flag
D
High-speed download flag
TR
1=TX Register Ready
Reserved
Table 10-10
shows the handshaking used when the
Intel® XScale™ Microarchitecture User's Manual
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7
6
5
4
3
2
1
0

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