Phy Unit Registers; Mdi Registers 0 - 7; Register 0: Control Register Bit Definitions - Intel GD82559ER Datasheet

9.

PHY Unit Registers

The 82559ER provides status and accepts management information via the Management Data
Interface (MDI) within the CSR space.
Acronyms mentioned in the registers are defined as follows:
SC -
RO -
E -
LL -
LH -
9.1

MDI Registers 0 - 7

9.1.1

Register 0: Control Register Bit Definitions

Bit(s)
15
14
13
12
11
10
Datasheet
self cleared
read only
EEPROM setting affects content
latch low
latch high
Name
Reset This bit sets the status and control register of the PHY to
their default states and is self-clearing. The PHY returns
a value of one until the reset process has completed and
accepts a read or write transaction.
1 = PHY Reset
Loopback This bit enables loopback of transmit data nibbles from
the TXD[3:0] signals to the receive data path. The PHY
unit's receive circuitry is isolated from the network.
Note that this may cause the descrambler to lose
synchronization and produce 560 nanoseconds of "dead
time."
Note also that the loopback configuration bit takes priority
over the Loopback MDI bit.
1 = Loopback enabled
0 = Loopback disabled (Normal operation)
Speed Selection This bit controls speed when Auto-Negotiation is disabled
and is valid on read when Auto-Negotiation is disabled.
1 = 100 Mbps
0 = 10 Mbps
Auto-Negotiation This bit enables Auto-Negotiation. Bits 13 and 8, Speed
Enable Selection and Duplex Mode, respectively, are ignored
when Auto-Negotiation is enabled.
1 = Auto-Negotiation enabled
0 = Auto-Negotiation disabled
Power-Down This bit sets the PHY unit into a low power mode. In low
power mode, the PHY unit consumes no more than 30
mA.
1 = Power-Down enabled
0 = Power-Down disabled (Normal operation)
Reserved This bit is reserved and should be set to 0b.
Networking Silicon — GD82559ER
Description Default R/W
0 RW
SC
0 RW
1 RW
1 RW
0 RW
0 RW
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