Master Operations; Master Transactions - Intel PXA255 Developer's Manual

2
I C Bus Interface Unit
9.4.6

Master Operations

When software initiates a read or write on the I
slave-receive mode to master-transmit mode. The 7-bit slave address and the R/nW bit follow the
start pulse. After the master receives an acknowledge, the I
•
Master-Transmit — I
•
Master-Receive — I
The CPU writes to the ICR register to initiate a master transaction. Data is read and written from
2
the I C unit through the memory-mapped registers.
responsibilities as a master device.
Table 9-5. Master Transactions (Sheet 1 of 2)
2
I C Master
Action
Generate clock
output
Write target
slave address
to IDBR
Write R/nW Bit
to IDBR
Signal START
Condition
Initiate first
data byte
transfer
Arbitrate for
2
I C Bus
9-12
2
C unit writes data
2
C unit reads data
Mode of
Operation
• Master drives the SCL line.
Master-transmit
• ICR[SCLE] bit must be set.
Master-receive
• ICR[IUE] bit must be set.
• CPU writes to IDBR bits 7-1 before a START condition enabled.
Master-transmit
• First seven bits sent on bus after START.
Master-receive
• See Section
• CPU writes to least significant IDBR bit with target slave address.
Master-transmit
• If low, master remains a master-transmitter. If high, master
transitions to a master-receiver.
Master-receive
• See Section
• See "Generate clock output" above.
• Performed after target slave address and R/nW bit are in IDBR.
Master-transmit
• Software sets ICR[START] bit.
Master-receive
• Software sets ICR[TB] bit to initiate start condition.
• See Section
• CPU writes byte to IDBR
Master-transmit 2
• I C unit transmits byte when ICR[TB] bit is set.
Master-receive 2
• I C unit clears ICR[TB] bit and sets ISR[ITE] bit when transfer is
complete.
• If two or more masters signal a start within the same clock period,
arbitration must occur.
2
• I C unit arbitrates for as long as needed. Arbitration takes place
during slave address and R/nW bit or data transmission and
continues until all but one master loses the bus. No data lost.
Master-transmit
2
• If I C unit loses arbitration, it sets ISR[ALD] bit after byte transfer is
Master-receive
completed and transitions to slave-receive mode.
2
• If I C unit loses arbitration as it attempts to send target address byte,
2
I C unit attempts to resend it when the bus becomes free.
• System designer must ensure boundary conditions described in
Section 9.4
2 2
C bus, the I C unit transitions from the default
2
C unit enters one of two master modes:
Table 9-5 describes the I
Definition
9.3.3.
9.4.2.
9.3.3.
do not occur.
Intel® PXA255 Processor Developer's Manual
2
C unit's