Mesi State Changes Resulting From Cpu Bus Operations; Read Hit; Read Miss - Intel 82496 CACHE CONTROLLER User Manual

COMPONENT OPERATION
READ MISS: NON·CACHEABLE
WRITE MISS: WRITE THRU
..( .... '--_ _ _ _ SNOOP.INV: BACK INVALIDATE
r - - - -
(CACHEABLE READ MISS + ALLOCATE).WT:
WRITE HIT.WT:
WRITETHRU
+ READ HIT
MODIFIED LINE
f l
~ L1NE FILL, WRITE BACK IF REPLACING
r-~M
SNOOP.!lNV.lNCA:
SNOOP.lNV:
1~~b~E
BACK INVALIDATE WRITE BACK
SNOOP.lNV:
INQUIRE
SNOOP WRITE BACK,
BACK INVALIDATE
ALLOCATE) IWT: L1NEFILL,
WRITE BACK IF REPLACING
' ' ' ' ' ' ' ' ' ' ' ' - , ..... ," . =,:,;.
W1RITE THRU
MODIRED LINE
4--------:--
WRITE HIT
----~
WRITE HIT
READ HIT
NOTES:
Wv~rt.~IEI~~~~
(OR SHARED)
NCA=NON CACHEING ACCESS
SNOOP.! INV.NCA:
INQUIRE
SNOOP WRITE BACK
ALLOCATE=WRITE MISS WHICH CAUSES LINE FILL
INQUIRE=SNOOP P51F 1M] STATE
LOCK, DRCTM, MRO, SYNC, FLUSH NOT SHOWN
I BEFORE THE TERM MEANS INACTIVE
Figure
3-1.
State Changes
SNOOP.IINV.NCA
READ
HIT
CDB5
3.5.1.
MESI State Changes Resulting From CPU Bus Operations
The MESI state of a valid 82496 Cache Controller/82491 Cache SRAM's line may change as
the controller services Pentium processor read and write requests.
3.5.1.1. READ HIT
A read hit occurs when the CPU requests a read cycle that can be serviced locally by the 82496
Cache Controller/82491 Cache SRAM using data present in the 82496 Cache Controller/82491
Cache SRAM. The MESI state of the cached line ([M], [E) or [S)) remains unchanged by this
operation.
3.5.1.2.
READ MISS
A read miss occurs when the CPU generates a read cycle that cannot be serviced locally
I
3·5