Rng Clocking; Error Management - ST STM32F423 Reference Manual

RM0430
To run the RNG in polling mode following steps are recommended:
1. Enable the random number generation by setting the RNGEN bit to "1" in the RNG_CR
register.
2. Read the RNG_SR register and check that:
–
–
3. If above conditions are true read the content of the RNG_DR register.
Note: When data is not ready (DRDY="0") RNG_DR returns zero.
Low-power operations
If the power consumption is a concern to the application, low-power strategies can be used,
as described in
Software post-processing
If a NIST approved DRBG with 128 bits of security strength is required an approved random
generator software must be built around the RNG true random number generator.
16.3.6

RNG clocking

The RNG runs on two different clocks: the AHB bus clock and a dedicated RNG clock.
The AHB clock is used to clock the AHB banked registers and the post-processing
component. The RNG clock is used for noise source sampling. Recommended clock
configurations are detailed in
Caution: When the CED bit in the RNG_CR register is set to "0", the RNG clock frequency must be
higher than AHB clock frequency divided by 16, otherwise the clock checker will flag a clock
error (CECS or CEIS in the RNG_SR register) and the RNG will stop producing random
numbers.
See Section 16.3.1: RNG block diagram
16.3.7

Error management

In parallel to random number generation an health check block verifies the correct noise
source behavior and the frequency of the RNG source clock as detailed in this section.
Associated error state is also described.
Clock error detection
When the clock error detection is enabled (CED = 0) and if the RNG clock frequency is too
low, the RNG stops generating random numbers and sets to "1" both the CEIS and CECS
bits to indicate that a clock error occurred. In this case, the application should check that the
RNG clock is configured correctly (see
the CEIS bit interrupt flag. As soon as the RNG clock operates correctly, the CECS bit will
be automatically cleared.
The RNG operates only when the CECS flag is set to "0". However note that the clock error
has no impact on the previously generated random numbers, and the RNG_DR register
contents can still be used.
No error occurred (the SEIS and CEIS bits should be set to '0')
A random number is ready (the DRDY bit should be set to '1')
Section 16.4: RNG low-power usage on page
Section 16.7: Entropy source
True random number generator (RNG)
for details (AHB and RNG clock domains).
Section 16.3.6: RNG
RM0430 Rev 8
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validation.
clocking) and then it must clear
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