Rng Clocking; Error Management - ST STM32F412 Reference Manual

True random number generator (RNG)
To run the RNG in polling mode following steps are recommended:
1. Enable the random number generation by setting the RNGEN bit to "1" in the RNG_CR
register.
2. Read the RNG_SR register and check that:
–
–
3. If above conditions are true read the content of the RNG_DR register.
Note: When data is not ready (DRDY="0") RNG_DR returns zero.
It is recommended to always verify that RNG_DR is different from zero. Because when it is
the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare
event).
Low-power operations
If the power consumption is a concern to the application, low-power strategies can be used,
as described in
Software post-processing
If a NIST approved DRBG with 128 bits of security strength is required an approved random
generator software must be built around the RNG true random number generator.
15.3.6

RNG clocking

The RNG runs on two different clocks: the AHB bus clock and a dedicated RNG clock.
The AHB clock is used to clock the AHB banked registers and the post-processing
component. The RNG clock is used for noise source sampling. Recommended clock
configurations are detailed in
Note: When the CED bit in the RNG_CR register is set to "0", the RNG clock frequency should be
higher than AHB clock frequency divided by 16, otherwise the clock checker always flags a
clock error (CECS=1 in the RNG_SR register).
See Section 15.3.1: RNG block diagram
15.3.7

Error management

In parallel to random number generation an health check block verifies the correct noise
source behavior and the frequency of the RNG source clock as detailed in this section.
Associated error state is also described.
Clock error detection
When the clock error detection is enabled (CED = 0) and if the RNG clock frequency is too
low, the RNG sets to "1" both the CEIS and CECS bits to indicate that a clock error
occurred. In this case, the application should check that the RNG clock is configured
correctly (see
flag. The CECS bit is automatically cleared when clocking condition is normal.
Note: The clock error has no impact on generated random numbers, i.e. application can still read
RNG_DR register.
CEIS is set only when CECS is set to "1" by RNG.
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No error occurred (the SEIS and CEIS bits should be set to 0)
A random number is ready (the DRDY bit should be set to 1)
Section 15.3.8: RNG low-power
Section 15.6: RNG entropy source
Section 15.3.6: RNG
usage.
for details (AHB and RNG clock domains).
clocking) and then it must clear the CEIS bit interrupt
RM0402 Rev 6
RM0402
validation.