Power Optimization In Run Mode; Dfsdm Interrupts - ST STM32F412 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
An injected conversion cannot be launched if another injected conversion is pending or
already in progress: any request to launch an injected conversion (either by JSWSTART or
by a trigger) is ignored as long as bit JCIP is '1' (in the DFSDM_FLTxISR register).
Similarly, a regular conversion cannot be launched if another regular conversion is pending
or already in progress: any request to launch a regular conversion (using RSWSTART) is
ignored as long as bit RCIP is '1' (in the DFSDM_FLTxISR register).
However, if an injected conversion is requested while a regular conversion is already in
progress, the regular conversion is immediately stopped and an injected conversion is
launched. The regular conversion is then restarted and this delayed restart is signalized in
bit RPEND.
Injected conversions have precedence over regular conversions in that a injected
conversion can temporarily interrupt a sequence of continuous regular conversions. When
the sequence of injected conversions finishes, the continuous regular conversions start
again if RCONT is still set (and RPEND bit will signalize the delayed start on the first regular
conversion result).
Precedence also matters when actions are initiated by the same write to DFSDM, or if
multiple actions are pending at the end of another action. For example, suppose that, while
an injected conversion is in process (JCIP=1), a single write operation to DFSDM_FLTxCR1
writes '1' to RSWSTART, requesting a regular conversion. When the injected sequence
finishes, the precedence dictates that the regular conversion is performed next and its
delayed start is signalized in RPEND bit.
14.4.18

Power optimization in run mode

In order to reduce the consumption, the DFSDM filter and integrator are automatically put
into idle when not used by conversions (RCIP=0, JCIP=0).
14.5

DFSDM interrupts

In order to increase the CPU performance, a set of interrupts related to the CPU event
occurrence has been implemented:
•
End of injected conversion interrupt:
–
–
–
–
•
End of regular conversion interrupt:
–
–
–
–
•
Data overrun interrupt for injected conversions:
–
374/1163
enabled by JEOCIE bit in DFSDM_FLTxCR2 register
indicated in JEOCF bit in DFSDM_FLTxISR register
cleared by reading DFSDM_FLTxJDATAR register (injected data)
indication of which channel end of conversion occurred, reported in JDATACH[1:0]
bits in DFSDM_FLTxJDATAR register
enabled by REOCIE bit in DFSDM_FLTxCR2 register
indicated in REOCF bit in DFSDM_FLTxISR register
cleared by reading DFSDM_FLTxRDATAR register (regular data)
indication of which channel end of conversion occurred, reported in
RDATACH[1:0] bits in DFSDM_FLTxRDATAR register
occurred when injected converted data were not read from DFSDM_FLTxJDATAR
register (by CPU or DMA) and were overwritten by a new injected conversion
RM0402 Rev 6
RM0402