Timx Counter (Timx_Cnt)(X = 16 To 17); Table 187. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature - ST STM32WL5 Series Reference Manual

General-purpose timers (TIM16/TIM17)

Table 187. Output control bits for complementary OCx and OCxN channels with break feature

Control bits
MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit
1 X
0
0
1
1. When both outputs of a channel are not used (control taken over by GPIO controller), the OISx, OISxN, CCxP and CCxNP
bits must be kept cleared.
Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and AFIO registers.
27.4.9

TIMx counter (TIMx_CNT)(x = 16 to 17)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
UIF
Res. Res. Res.
CPY
r
15 14 13
rw rw rw
940/1461
X 0 0
0 0 1
0 1 0
X 1 1
1 0 1
1 1 0
X X
0 0
0 1
X
1 0
1 1
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
(TIM16/17)
OCx output state
Output Disabled (not driven by the timer: Hi-Z)
OCx=0
OCxN=0, OCxN_EN=0
Output Disabled (not driven
by the timer: Hi-Z)
OCx=0
OCxREF + Polarity
OCx=OCxREF XOR CCxP
OCREF + Polarity + dead-
time
Off-State (output enabled
with inactive state)
OCx=CCxP
OCxREF + Polarity
OCx=OCxREF XOR CCxP,
OCx_EN=1
Output disabled (not driven by the timer: Hi-Z).
Off-State (output enabled with inactive state)
Asynchronously: OCx=CCxP, OCxN=CCxNP
Then if the clock is present: OCx=OISx and OCxN=OISxN
after a dead-time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state
24 23 22
Res. Res. Res.
8 7 6
CNT[15:0]
rw rw rw
RM0453 Rev 1
(1)
Output states
OCxN output state
OCxREF + Polarity
OCxN=OCxREF XOR CCxNP
Output Disabled (not driven by
the timer: Hi-Z)
OCxN=0
Complementary to OCREF (not
OCREF) + Polarity + dead-time
OCxREF + Polarity
OCxN=OCxREF XOR CCxNP
Off-State (output enabled with
inactive state)
OCxN=CCxNP, OCxN_EN=1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
RM0453
17 16
Res. Res.
1 0
rw rw