Timx Counter (Timx_Cnt); Timx Prescaler (Timx_Psc); Timx Auto-Reload Register (Timx_Arr) - ST STM32F207 Series Reference Manual

RM0033
Note: The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
14.4.10

TIMx counter (TIMx_CNT)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:16 CNT[31:16]: High counter value (on TIM2 and TIM5).
Bits 15:0 CNT[15:0]: Low counter value
14.4.11

TIMx prescaler (TIMx_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
14.4.12

TIMx auto-reload register (TIMx_ARR)

Address offset: 0x2C
Reset value: 0xFFFF FFFF
31 30 29
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15 14 13
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28 27 26 25
CNT[31:16] (depending on timers)
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12 11 10 9
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12 11 10 9
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The counter clock frequency CK_CNT is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in "reset mode").
28 27 26 25
ARR[31:16] (depending on timers)
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12 11 10 9
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General-purpose timers (TIM2 to TIM5)
24 23 22
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8 7 6
CNT[15:0]
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8 7 6
PSC[15:0]
rw rw rw
24 23 22
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8 7 6
ARR[15:0]
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RM0033 Rev 9
21 20 19 18
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5 4 3 2
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5 4 3 2
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/ (PSC[15:0] + 1).
CK_PSC
21 20 19 18
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5 4 3 2
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17 16
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1 0
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1 0
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17 16
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1 0
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