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msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bit
Name
0:22
—
23
SEAE
24
MME
25
TTAE
26
TTRE
27
ECWE
28
TTME
29
BAE
30
DTE
31
ATE
16.2.5
Arbiter Address Capture Register (R)—MBAR + 0x1F50
The Arbiter Address Capture Register captures the address for a tenure that has either:
•
an address time-out,
•
a data time-out, or
•
a TEA from another source
The captured value is held until unlocked by writing any value to the Arbiter Address Capture Register or Arbiter Bus Signal Capture Register.
This value is also unlocked by writing a 1 to either the Arbiter Status Register, bit 30 (Data Tenure Time-out Status) or bit 31 (Address Tenure
Time-Out Status). Unlocking the register does not clear its contents.
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Freescale Semiconductor
Table 16-4. Arbiter Interrupt Enable Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
Rsvd
0
0
0
0
0
Reserved
Slave Error Acknowledge interrupt enable
Multiple Masters at priority 0 interrupt enable
TT Address Only interrupt enable
TT Reserved interrupt enable
External Control Word Read/Write interrupt enable
TBST/TSIZ mismatch interrupt enable
Bus Activity Tenure Time-out interrupt enable
Data Tenure Time-out interrupt enable
Address Tenure Time-out interrupt enable
Table 16-5. Arbiter Address Capture Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
XLB Arbiter Registers—MBAR + 0x1F00
7
8
9
10
Rsvd
0
0
0
0
23
24
25
26
SEAE MME TTAE
TTRE ECWE TTME BAE
0
0
0
0
Description
7
8
9
10
Address[0:15]
0
0
0
0
23
24
25
26
Address[16:31]
0
0
0
0
11
12
13
14
0
0
0
0
27
28
29
30
31 lsb
DTE
0
0
0
0
11
12
13
14
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
15
0
ATE
0
15
0
0
16-7
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