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PSC Operation Modes
CDM
Mclk
f
system
Divider
MclkDiv[8:0]+1
IPB
Interface
CommBus
Interface
IRQ
Controller
BestComm
Request
For MIR and FIR mode the clock for the transmitter and receiver is generated by dividing down from the internal Mclk or from an external
clock. If the bit GenClk in the
SICR
goes through a pre-divider to the clock generator. See
Infrared FIR Divide Register (0x54)—IRFDR
Section 5.5.11, PSC1 Mclock Config Register—MBAR +
for the clock generation.
If the
CCR
2. This is the minimum value. 0x00 deactivate the clock generation.
15.3.4.2.2
Transmitting and Receiving in MIR Mode
Each bit data is encoded so that a 0 is encoded as 1/4 of the bit time pulse and a 1 is encoded as no pulse. Similarly, the received serial pulse
is decoded as a 0 and an absence of a pulse is decoded as a 1. The PSC MIR mode use the HDLC bit stuffing after five consecutive ones to
decode/encode the data, except the STA and STO flag. For example see the Figure below:
binary data
0
The packet format is:
STA
01111110
15-68
PSC
Clock
divider
Mclk
BitClkDiv[0:7]+1
SICR[GenClk]
Rx FIFO
Tx FIFO
Figure 15-19. PSC MIR and FIR Block Diagram
was set to "1" then PSC generate the clock from the internal source. The clock from the Mclk generator
Section 15.2.26, Infrared MIR Divide Register (0x50)—IRMDR
for the possible frequencies for this mode. For more informations about the Mclk divider see
0x0228. If the bit GenClk cleared then the PSC use the clock from an external source
register was not changed (reset value 0x01) then the counter divide the clock (Mclk) by
Flag
1
1
1
1
1
1
0
1/4 of the bit width
STA
01111110
MPC5200B Users Guide, Rev. 1
Clock
Generation
0
1
Unit
IrdaClk
IRMDR[1:7] for MIR mode
IRFDR[4:7] for FIR mode
Receiver
Transmitter
NOTE
character FE
0
1
1
1
1
1
0
This zero was insert after five
consecutive ones!
DATA
FCS
DATA
16 bit CRC
IR_USB_CLK
IRDA_RX
External
Interface
Signals
IRDA_TX
or
Section 15.2.27,
1
1
0
1
0
1
STO
01111110
Freescale Semiconductor
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