Freescale Semiconductor MPC5200B User Manual page 567

PSC Operation Modes
15.3.2.5 Transmitting and Receiving in "Cell Phone" Mode
The transmission protocol for the "Cell Phone" mode is the same like in the "Soft Modem" mode. The PSC use the configure and clock
generation registers is the same as described in the section before, see
Mode. The goal for this mode is, that PSC2, 3 or 6 can generate a BitClk which is synchronous to in the BitClk input on PSC1. Only the
internal clock distribution is different to the "Soft Modem" mode. The major deviation is, that the "Cell Phone" slave PSCs use the clock from
PSC1 for BitClk and FrameSync generation instead of Mclk from the CDM module.
PSC1 is the only PSC that can work as "Cell Phone" master, PSC2, 3 or 6 are available as "Cell Phone" slave. The "Cell Phone" master PSC
must be configured as codec slave, this means that the PSC1 receive the BitClk from the outside. Therefore the SICR[GenClk] bit must be
cleared. The "Cell Phone" slave PSCs must be configured as codec master. Therefore the SICR[GenClk] must be set and the FrameSyncDiv
and BitClkDiv values in the CCR
Generation. To enable the "Cell Phone" slave functionality the SICR[CellSlave] bit must set. If this bit was set the PSCs use the BitClk from
PSC1 for the internal clock generation instead of the Mclk. If the SICR[CellSlave] and the SICR[Cell2xClk] bit was set, then the "Cell Phone"
salve PSCs use the BitClk from PSC1 multiplied by 2 for the internal clock generation. These facts are described in
Table 15-82 and Table 15-83 shows an example how to configure the PSC system as follows:
• PSC1 is "Cell Phone" master, PSC2 works as "Cell Phone" slave
• both PSC work with 24bit data
• Data are sampled on the falling edge of BitClk
• FrameSync is high true
• MSB first, transfer starts on the leading edge of FrameSync
• PSC2 us the BitClk from PSC1 multiplied by 2 for clock generation
• FrameSync every 24BitClk, for both PSCs
• set FrameSync width to 1 BitClk
• set the TFALARM level to 0x010, alarm occurs if 16 byte are in the TxFIFO
• set the RFALARM level to 0x00C, alarm occurs if 12 byte space in the RxFIFO
• enable TxRDY interrupt
BitClk
Frame
PSC 1
BitClk
Clock
Frame Gener-
ation
PSC 2,3 or 6
Figure 15-11. Clock distribution network in cell phone mode
15-56
register must be set to the desired value, like described in
Clock
multiply by 2
Mclk (not used)
MPC5200B Users Guide, Rev. 1
Section 15.3.2.3, Transmitting and Receiving in "Soft Modem" Codec
Section 15.3.2.2, Codec Clock and FrameSync
PSC1 configured as slave
but called "cell phone master"
PSC2, 3 or 6.
SICR[GenClk] = 0, slave mode
PSC2, 3 or 6 configured as master, provide BitClk and
Frame, but called "cell phone slave", receive clock
from PSC1.
SICR[GenClk] = 1, master mode
SICR[CellSlave] = 1, use clock from PSC1 (normal or
double clock)
SICR[Cell2xClk] = 0, use normal clock
SICR[Cell2xClk] = 1, use double clock
Figure 15-11
—
receive BitClk and Frame,
—
provide clock to
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