Rx Status Pcirsr (R/Sw1) —Mbar + 0X389C - Freescale Semiconductor MPC5200B User Manual

Registers
Bits Name
0:31 Packets_Done
10.3.3.2.9 Rx Status PCIRSR (R/sw1) —MBAR + 0x389C
msb 0 1
R
W
RESET 0 0
16 17
R
W
RESET 0 0
Bits Name
0:6 Reserved
7 Normal
Termination
(NT)
8 Bus Error
type 3
(BE3)
9 Bus Error
type 2
(BE2)
10 Bus Error
type 1
(BE1)
11 FIFO Error
(FE)
10-40
This status register indicates the number of packets received. It is active only if continuous
mode is in effect. If the following occurs, the counter is reset:
• Reset Controller bit, PCIRER[RC], is asserted (normal way to restart continuous mode)
• Master Enable bit, PCIRER[ME], is negated
In this way, master enable can be used to reset Packets_Done status without disturbing
continuous mode addressing. At any point in time the total number of Bytes received can
be calculated as:
(Packets_Done x Packet_Size) + Bytes_Done
This assumes Packet_Size is the same for all restart sequences.
2 3 4 5 6
Reserved
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
Unused. Software should write zero to these bits.
This flag is set when any packet terminates normally. It is not set in the case of an
abnormally terminated packet. It does not require clearing but will not clear until it is written
to a one (in which case it will now read back as zero, i.e. negated).
>ALL THE FOLLOWING FLAG BITS OPERATE SIMILARLY<
This flag is set whenever a Slave bus transaction attempts to write to a Read-Only register.
This flag bit is set regardless of the Bus error Enable bit (BE). If software is polling this Byte
and wishes to disregard this error it must mask this bit out. No corruption of the register bits
occur for this (or any other) Bus Error case.
This flag is set whenever a Slave bus transaction attempts to write to a Reserved register
(an entire 32-bit register, not just a Reserved bit or byte). This flag bit is set regardless of
the Bus error Enable bit (BE). If software is polling this Byte and wishes to disregard this
error it must mask this bit out.
This flag is set whenever a Slave bus transaction attempts to read a Reserved register (an
entire 32-bit register, not just a Reserved bit or byte). This flag bit is set regardless of the
Bus error Enable bit (BE). If software is polling this Byte and wishes to disregard this error
it must mask this bit out.
This flag is set whenever the Receive FIFO asserts its FIFO Error output. A CPU interrupt
will be generated if the FIFO Error Enable (FEE) bit is set. The source of the error must be
determined by reading the FIFO Error status register. Also, the error condition must be
cleared at the FIFO prior to clearing this Sticky bit or this flag will continue to assert.
MPC5200B Users Guide, Rev. 1
Description
7 8 9 10
NT BE3 BE2 BE1
rwc rwc rwc rwc rwc
0 0 0 0
23 24 25 26
Reserved
0 0 0 0
Description
11 12 13 14 15
FE SE RE TA IA
rwc rwc rwc rwc
0 0 0 0
27 28 29 30 31 lsb
0 0 0 0
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