Cdm Clock Control Sequencer Configuration Register—Mbar + 0X021C - Freescale Semiconductor MPC5200B User Manual

CDM Registers
16 17
R
W
RESET: 0 0
Bit Name
0–6 —
7 sys_osc_disable
8–31 —
5.5.8 CDM Clock Control Sequencer Configuration Register—MBAR + 0x021C
This register contains the configuration that controls the CCS module. The CCS module lets MPC5200B enter deep sleep power down mode
(all clocks stopped).
Table 5-15. CDM Clock Control Sequencer Configuration Register
msb 0 1
R
W
RESE 0 0
T:
16 17
R
W
RESE 0 0
T:
Bit Name
0–6 —
7 ccs_sleep_en
8–14 —
15 ccs_osc_sleep_en
5-18
18 19 20 21
0 0 0 0
Reserved for future use. Write 0.
CDM System Oscillator Disable
bit=1:System Oscillator is disabled. External clock source is required.
bit=0:System Oscillator is enabled. 27–33MHz crystal is being used.
Reserved for future use. Write 0.
2 3 4 5
Reserved
Write 0
0 0 0 0
18 19 20 21 22
0 0 0 0
Reserved for future use. Write 0.
CCS Module Enable
bit=1:CCS enabled. e300 Core QREQ signal triggers deep sleep cycle.
bit=0:CCS disabled and inactive. No deep sleep mode possible.
Note: This bit should only be set before the processor should go into deep sleep
mode. And it should be reseted after wake up.
Note: It is not allowed to set this bit if a JTAG debugger or the nap mode should be
used.
Reserved for future use. Write 0.
CCS System Oscillator Disable Control
bit=1:CCS can disable System Oscillator in deep sleep mode.
bit=0:CCS cannot disable System Oscillator in deep sleep mode. Oscillator
remains active.
MPC5200B Users Guide, Rev. 1
22 23 24 25 26
Reserved
Write 0
0 0 0 0
Description
6 7 8 9 10
0 0 0 0 0
23 24 25 26
Reserved
Write 0
0 0 0 0 0
Description
27 28 29 30
0 0 0 0 0
11 12 13 14
Reserved
Write 0
0 0 0 0
27 28 29 30
0 0 0 0
Freescale Semiconductor
31 lsb
0
15
0
31 lsb
1