Target Abort; Latrule Disable; Communication Sub-System Initiator Interface - Freescale Semiconductor MPC5200B User Manual

Table 10-12. Non-contiguous PCI to XL bus Transfers (require two XL Bus bus accesses)
PCI Bus
BE
AD[2:0] 31:24 23:16
[3:0]
1010 000
1010 100
0110 000 OP3
0110 100 OP3
0101 000 OP3
0101 100 OP3
0010 000 OP3
0010 100 OP3
0100 000 OP3
0100 100 OP3
10.4.5.4

Target Abort

A target abort will occur if the PCI address falls within a base address window (BAR0 or BAR1) that has not been enabled.
Target Base Address Translation Register 0 PCITBATR0(RW) —MBAR + 0x0D64
Translation Register 1 PCITBATR1(RW) —MBAR +
10.4.5.5

Latrule Disable

The latrule disable bit in the interface control register,
prevents the PCI controller from automatically disconnecting a target transaction due to the PCI 16/8 clock rule. With this bit set, it is possible
to hang the PCI bus if the internal bus does not complete the data transfer.
10.4.6

Communication Sub-System Initiator Interface

This interface provides for high-speed, autonomous DMA transactions to PCI with the PCI Controller operating as a standard Communication
Sub-System peripheral. Full duplex operation is supported and direct XL bus transactions can also be interleaved while CommBus
transactions are in progress. Internal arbitration will occur continuously to support transaction interleaving.
Arbitration.) Multi-Channel DMA operation operates independently of the XL bus. Non-PCI transactions on the XL bus will have 100%
bandwidth available to them during PCI Multi-Channel DMA activities. In general, this block will be used by functions in the Multi-Channel
DMA API.
Freescale Semiconductor
15:8 7:0 A[29:31]
OP3 OP2 000
010
OP3 OP2 100
110
OP2 000
011
OP2 100
111
OP2 001
011
OP2 101
111
OP2 OP1 000
010
OP2 OP1 100
110
OP2 OP1 000
011
OP2 OP1 100
111
0x0D68.
Section 10.3.2.4, Target Control Register PCITCR(RW) —MBAR +
MPC5200B Users Guide, Rev. 1
XL bus
Data Bus Byte Lanes
0 1 2 3
OP2
OP3
OP2
OP2
OP3
OP2
OP2
OP3
OP1
OP2 OP3
OP1
OP1 OP2
OP3
OP1
and
Section 10.3.2.3, Target Base Address
Functional Description
4 5 6 7
OP3
OP3
OP2
OP3
OP2 OP3
OP2
OP3
Section 10.3.2.2,
0x0D6C,
(Section 10.4.2, Initiator
10-59