Freescale Semiconductor MPC5200B User Manual page 166

7.2.4.2 ICTL Peripheral Priority and HI/LO Select 1 Register —MBAR + 0x0504
Table 7-5. ICTL Peripheral Priority and HI/LO Select 1 Register
msb 0 1
R Per0_pri
W
RESET: 0 0
16 17
R Per4_pri
W
RESET: 0 0
Bits Name
— Per[x]_pri
0:3 Per0_pri
4:7 Per1_pri
8:11 Per2_pri
12:15 Per3_pri
16:19 Per4_pri
20:23 Per5_pri
24:27 Per6_pri
28:31 Per7_pri
Note:
1. Per0_pri, associated with the BestComm interrupt source, is not programmable and always has the highest peripheral
priority and always results in a HI interrupt condition to the Interrupt Controller. These bits are writable and readable, but
have no effect on controller operation.
Freescale Semiconductor
2 3 4 5 6
Per1_pri
0 0 0 0 0
18 19 20 21 22
Per5_pri
0 0 0 0 0
Priority encoding is done using 4 configuration bits per input source. Each group of 4bits
controls the source priority in relation to other peripheral sources. The most significant bit
(msb) of each config nibble is called the HI/LO or "bank" bit.
If this bit is high it implies not only a high priority, but causes this interrupt source to assert a
HI interrupt condition. Under most circumstances this creates a Critical Interrupt assertion to
the e300 core. See Note 1.
Peripherals with identical priority settings (either zero or non-zero) are default prioritized with
"lower peripheral has higher priority". In other words, Per1 has a default priority higher than
Per2.
Peripheral 0 = BestComm interrupt (fixed as highest peripheral)
Peripheral 1 = PSC1 interrupt source
Peripheral 2 = PSC2
Peripheral 3 = PSC3
Peripheral 4 = PSC6
Peripheral 5 = Ethernet
Peripheral 6 = USB
Peripheral 7 = ATA
MPC5200B Users Guide, Rev. 1
7 8 9 10 11
Per2_pri
0 0 0 0
23 24 25 26 27
Per6_pri
0 0 0 0
Description
Interrupt Controller
12 13 14 15
Per3_pri
0 0 0 0 0
28 29 30 31 lsb
Per7_pri
0 0 0 0 0
7-7