Freescale Semiconductor MPC5200B User Manual page 538

Bit Name
0 AC97 CMD
1:7 AC97 Control
Register Index
6:23 AC97 Command
Data
24:31 —
15.2.17 AC97 Status Data Register (0x2C)—AC97Data
This read-only register contains the received response of a AC97 read command. If this register contains new data then the SR[DATA_VALID]
will be set to one by the receiver. A read access to this register cleared the SR[DATA_VALID] bit.
0 1 2
R AC97 Register Index Echo
W
RESET: 0 0 0
16 17 18
R AC97 Control Register Read Data[7:0]
W
RESET: 0 0 0
Bit Name
0 —
1:7 AC97 Register
Index Echo
6:23 AC97 Control
Register
ReadData
24:31 —
15.2.18 Interrupt Vector Register (0x30)—IVR
This register is not used since the MPC5200 does not use interrupt vectors supplied by the peripherals.
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
Enhanced AC97 Mode—AC97 Command
This bit indicates if the access to the Control Register is a read or write access. It will
be paste to the Slot1 bit 19.
0 = write access
1 = read access
other Modes—Reserved
Enhanced AC97 Mode—AC97 address Register
This register contains target control register address. It will be paste to the Slot1 bit
18 to 12.
other Modes—Reserved
Enhanced AC97 Mode—AC97 Command Data Register
This register is used define the command data value for a write command. It will be
paste to the Slot2 bit 19 to 4.
other Modes—Reserved
Reserved
Table 15-37. AC97 Status Data Register (0x2C)—AC97Data
3 4 5 6
0 0 0 0
19 20 21 22
0 0 0 0
Reserved
Enhanced AC97 Mode—AC97 Register Index Echo
This register contains the received Register Index Echo from the RX Slot0.
other Modes—Reserved
Enhanced AC97 Mode—AC97 Control Register Read Data
This register contains the received control data from Rx Slot2.
other Modes—Reserved
Reserved
MPC5200B Users Guide, Rev. 1
Description
7 8 9 10 11
AC97 Control Register Read Data[15:8]
erved
Res
0 0 0 0
23 24 25 26 27
erved
Res
0 0 0 0
Description
12 13 14 15 lsb
0 0 0 0 0
28 29 39 31
Reserved
0 0 0 0 0
15-27