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The R_DES_ACTIVE bit is cleared at reset and by the clearing of ETHER_EN.
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:6
—
7
R_DES_ACTIVE Set to one when this register is written, regardless of the value written. Cleared by the
8:31
—
14.5.5
FEC Tx Descriptor Active Register—MBAR + 0x3014
The FEC descriptor active register is a command register which should be written by the user to indicate that the transmit descriptor ring has
been updated (transmit buffers have been produced by the driver with the R bit set in the buffer descriptor).
Whenever the register is written the X_DES_ACTIVE bit is set. This is independent of the data actually written by the user. When set, the
FEC will poll the transmit descriptor ring and process transmit frames (provided ETHER_EN is also set). Once the FEC polls a transmit
descriptor whose ownership bit is not set, then the FEC will clear the X_DES_ACTIVE bit and cease transmit descriptor ring polling until the
sets the bit again, signifying additional descriptors have been placed into the transmit descriptor ring.
The X_DES_ACTIVE bit is cleared at reset and by the clearing of ETHER_EN.
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Freescale Semiconductor
Table 14-12. FEC Rx Descriptor Active Register
2
3
4
5
6
Reserved
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Reserved
FEC device whenever no additional "ready" descriptors remain in the receive ring.
Reserved
Table 14-13. FEC Tx Descriptor Active Register
2
3
4
5
6
Reserved
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
7
8
9
10
11
0
0
0
0
23
24
25
26
27
Reserved
0
0
0
0
Description
7
8
9
10
11
0
0
0
0
23
24
25
26
27
Reserved
0
0
0
0
FEC Registers—MBAR + 0x3000
12
13
14
15
Reserved
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
12
13
14
15
Reserved
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
14-15
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