Freescale Semiconductor MPC5200B User Manual page 319

Registers
10.3.2.10 Initiator Status Register PCIISR(RWC) —MBAR + 0x0D88
msb 1
0
R Reserved
W
RESET 0 0
16 17
R
W
RESET 0 0
Bits Name
0:4 Reserved
5 Retry
Error
(RE)
6 Initiator Abort
(IA)
7 Target Abort
(TA)
8:31 Reserved
10.3.2.11 PCI Arbiter Register PCIARB(RW) —MBAR + 0x0D8C
msb 0 1
R
W
RESET 0 0
16 17
R
W
RESET 0 0
Bits Name
0:6 Reserved
10-22
2 3 4 5 6
RE IA
rwc rwc
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
Unused bits. Software should write zero to this register.
This flag is set if Max_Retries is set to a finite value (0x01 through 0xff) and the Target has
performed Max_Retries number of retry disconnects for a single transaction. A retry error
would generally indicate a broken or improperly accessed Target. A CPU interrupt will be
generated if PCIICR[RE] bit is set. This is a RWC (Read/WriteClear) bit: to clear it, software
must write a '1' at this position.
This flag bit is set if the PCI controller issues an Initiator Abort flag. This indicates that no
Target responded by asserting DEVSEL within the time allowed for subtractive decoding. A
CPU interrupt will be generated if the PCIICR[IAE] bit is set. This is a RWC
(Read/WriteClear) bit: to clear it, software must write a '1' at this position.
This flag bit is set if the addressed PCI Target has signalled an Abort. A CPU interrupt will
be generated if the PCIICR[TAE] bit is set. It is up to application software to query the
Target's status register and determine the source of the error. This is a RWC
(Read/WriteClear) bit: to clear it, software must write a '1' at this position.
Unused bits. Software should write zero to this register.
2 3 4 5
Reserved
0 0 0 0
18 19 20 21 22
0 0 0 0 0
Unused bits. Software should write zero to this register.
MPC5200B Users Guide, Rev. 1
7 8 9 10
TA
rwc
0 0 0 0
23 24 25 26
Reserved
0 0 0 0
Description
6 7 8 9 10
ASR
0 0 0 0 0
23 24 25 26
Reserved
0 0 0 0
Description
11 12 13 14 15
Reserved
0 0 0 0 0
27 28 29 30 31 lsb
0 0 0 0 0
11 12 13 14 15
Reserved
0 0 0 0 0
27 28 29 30 31 lsb
0 0 0 0 0
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