Memory Pointer Partition—Mbar + 0X1018 - Freescale Semiconductor MPC5200B User Manual

Host Control (HC) Operational Registers
16 17
R
W
RESET: 0 0
Bits Name
0 MIE
1 OC
2:24 —
25 RHSC
26 FNO
27 UE
28 RD
29 SF
30 WDH
31 SO
12.4.3 Memory Pointer Partition—MBAR + 0x1018
This HC partition uses 7 32-bit registers. These registers are located at an offset from MBAR of 0x1018. Register addresses are relative to
this offset. Therefore, the actual register address is:
The following registers are available:
• USB HC HCCA Register
• USB HC Period Current Endpoint Descriptor Register
• USB HC Control Head Endpoint Descriptor Register
• USB HC Control Current Endpoint Descriptor Register
• USB HC Bulk Head Endpoint Descriptor Register
12-12
18 19 20 21 22
Reserved
0 0 0 0 0
Master Interrupt Enable—bit is set after a hardware or software reset.
0 written to this bit is ignored by HC.
1 written to this bit disables interrupt generation, due to events specified in other bits of this
register.
OwnershipChange
Ignore
Disable interrupt generation due to Ownership Change
Reserved
RootHubStatusChange
Ignore
Disable interrupt generation due to root hub status change.
FrameNumberOverflow
Ignore
Disable interrupt generation due to frame number overflow.
UnrecoverableError
Ignore
Disable interrupt generation due to unrecoverable error.
ResumeDetected
Ignore
Disable interrupt generation due to resume detect.
StartofFrame
Ignore
Disable interrupt generation due to start of frame.
WritebackDoneHead
Ignore
Disable interrupt generation due to HcDoneHead writeback.
SchedulingOverrun
Ignore
Disable interrupt generation due to scheduling overrun.
MBAR + 0x1018 + register address
(0x1018)
(0x1028)
MPC5200B Users Guide, Rev. 1
23 24 25 26
RHSC FNO
0 0 0 0
Description
(0x101C)
(0x1020)
(0x1024)
27 28 29 30 31 lsb
UE RD SF WDH SO
0 0 0 0
Freescale Semiconductor
0