Freescale Semiconductor MPC5200B User Manual page 548

Bit Name
0:3 —
4:7 F_FDIV
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
Reserved
FIR—Clock divide ratio in FIR mode.
The bit frequency is derived by:
This bit frequency should be 8 MHz. In order to receive the minimum pulse width described in
the IrDA spec, (F_FDIV + 1) should be larger than or equal to 4.
frequency selection. For more informations about the frequency generation see also
Section 15.2.14, Codec Clock Register (0x20)—CCR
15-19,
other Modes—Reserved
Table 15-56. Frequency Selection for FIR Mode
F_FDIV[3:0]
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
...
MPC5200B Users Guide, Rev. 1
Description
f IrdaClk
f bit =
----------------------------- -
F_FDIV + 1
and
Frequency of IrdaClk [MHz]
32.0
40.0
48.0
56.0
64.0
72.0
80.0
88.0
...
Table 15-56 shows several
Figure
Section 15.3.4.3, PSC in FIR Mode.
15-37