Freescale Semiconductor MPC5200B User Manual page 314

Bits Name
0:1 Base Address
Translation 1
2:30 Reserved
31 Enable 1
10.3.2.4 Target Control Register PCITCR(RW) —MBAR + 0x0D6C
msb 1
0
R
W
RESET 0 0
16 17
R
W
RESET 0 0
Bits Name
0:6 Reserved
7 Latrule
Disable
(LD)
8:14 Reserved
15 Prefetch Reads
(P)
16:22 Reserved
Freescale Semiconductor
This base address register corresponds to a hit on the BAR1 in MPC5200B PCI Type 0
Configuration space register (PCI space). When there is a hit on MPC5200B PCI BAR1
(MPC5200B as Target), the upper 2 bits of the external PCI address (1Gbyte boundary)
are written over by this register value to address some 1Gbyte space in MPC5200B. This
register can be reprogrammed to move the window of MPC5200B address space
accessed during a hit in PCIBAR1. It should be written by software during initialization to
point to the internal SDR/DDR memory space.
Note: This register should not point to the LocalPlus Memory Space. This is not
supported.
Unused bits. Software should write zero to this register.
This bit enables a transaction in BAR1 space. If this bit is zero and a hit on MPC5200B
PCI BAR1 occurs, the target interface gasket will abort the PCI transaction.
2 3 4 5 6
Reserved
0 0 0 0 0
18 19 20 21 22
Reserved
0 0 0 0 0
Unused bits. Software should write zero to this register.
This control bit applies only when MPC5200B is Target. When set, it prevents the PCI
Controller from automatically issuing a retry disconnect due to the PCI 16/8 clock rule.
The bit must be set before the 15th PCI clock for the first transfer and before the 7th clock
for other transfers.
Unused bits. Software should write zero to this register.
This bit controls fetching a line from memory in anticipation of a request from the external
master. The target interface will continue to prefetch lines from memory as long as
PCI_FRAME is asserted and there is space to store the data in the target read buffer.
Note: This bit only applies to PCI reads in the address range for BAR 1 (prefetchable
memory).
Note: Prefetching is performed in response to a PCI memory-read-multiple command even
if this bit is cleared.
Unused bits. Software should write zero to this register.
MPC5200B Users Guide, Rev. 1
Description
7 8 9 10 11
LD Reserved
0 0 0 0
23 24 25 26 27
WC
Write Combine Timer [7:0]
D
0 0 0 0
Description
Registers
12 13 14 15
P
0 0 0 0 0
28 29 30 31 lsb
0 1 0 0 0
10-17