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Bits
Name
6
IE
Enables drive interrupt to pass to CPU in PIO modes.
7
IORDY
Set by software when the drive supports IORDY. Required for PIO mode 3 and above.
16:31
—
Reserved
11.3.1.2
ATA Host Status Register—MBAR + 0x3A04
msb 0
1
R
TIP
UREP
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0
TIP
1
UREP
2:5
—
6
RERR
7
WERR
8:31
—
11.3.1.3
ATA PIO Timing 1 Register—MBAR + 0x3A08
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Freescale Semiconductor
Table 11-2. ATA Host Status Register
2
3
4
5
6
Reserved
RERR
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Transaction in Progress—indicator bit MUST be polled by software before PIO access.
System bus (XL bus) locks up if PIO access is attempted while this bit is set. This bit is
read-only.
UDMA Read Extended Pause—bit sets when drive stops strobing for an extended period
without initiating burst termination by negating DMARQ, during an UDMA read burst.
Software may initiate an Ultra DMA read burst termination, in this case by setting ATA Drive
Device Command Register HUT bit (see
Reserved
Read Error—An un-implemented register read.
Write Error—An un-implemented register write.
Reserved
Table 11-3. ATA PIO Timing 1 Register
2
3
4
5
6
pio_t0
0
0
0
0
0
18
19
20
21
22
pio_t2_16
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
Description
7
8
9
10
WERR
0
0
0
0
23
24
25
26
Reserved
0
0
0
0
Description
Table
11-29.).
7
8
9
10
11
0
0
0
0
23
24
25
26
27
0
0
0
0
ATA Register Interface
11
12
13
14
15
Reserved
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
12
13
14
15
pio_t2_8
0
0
0
0
0
28
29
30
31 lsb
Reserved
0
0
0
0
0
0
0
11-3
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