Freescale Semiconductor MPC5200B User Manual page 262

The Figure 8-3. Programmable Command Timings shows the timings which can be programmed by the two Controller Configuration
Register. The timing diagram uses the suggested values for a DDR memory and a 132 MHz memory clock. The displayed Commands are the
limiting cases.
MEM_CLK
Read Bstrm
CL
Read
CL
Read
Write
Write
pre2act + 1
Prech
act2rw + 1
Active
Ref
Freescale Semiconductor
(srd2rwp +1)
Write
wr_latency/3
(srd2rwp +1) or (brd2wt + 1)
brd2rp + 1
swt2rwp + 1
Prech
bwt2rwp + 1
Active
Read
ref2act + 1
Figure 8-3. Programmable Command Timings
MPC5200B Users Guide, Rev. 1
Memory Controller Registers (MBAR+0x0100:0x010C)
Single Read to Read/Write/Precharge
Burst Read to Write/Precharge
Write
wr_latency/3
Read
Single Write to Read/Write/Precharge
Burst Write to Read/Write/Precharge
Prech
Data
Data
Burst Read to Read
Precharge to Active/Refresh
Active to Read/Write
Refresh to Active
Active
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