Block Diagram And Signal Definition For Codec Mode - Freescale Semiconductor MPC5200B User Manual

PSC Operation Modes
15.3.2.1

Block Diagram and Signal Definition for Codec Mode

CDM
f
Mclk
system
Divider
MclkDiv[8:0]+1
IPB
Interface
CommBus
Interface
IRQ
Controller
Here is important difference between PSC6 and the other PSCs. To work with PSC6 in slave mode
(CODEC slave, SPI slave), the ext_48MHz_en bit in the
cdm_48mhz_fractional_divider_configuration register must be set to one. If this bit was set to zero
then the internal 48 Mhz clock generator drive the clock line. For more informations see
CDM 48MHz Fractional Divider Configuration Register—MBAR +
15-50
PSC
Clock
Mclk
Generation
Unit
BitClkDiv[0:15]+1
Rx FIFO
Tx FIFO
Figure 15-6. PSC Codec Block Diagram
NOTE
PSC
FRAME
CLK
TxD
RxD
Figure 15-7. PSC Codec Interface in Slave Mode
MPC5200B Users Guide, Rev. 1
Mclk
BitClk
Frame
RxD
Receiver
TxD
Transmitter
Section 5.5.5,
0x0210.
external
Codec device
SSYNC0
SCLK0
SRx0
STx0
Freescale Semiconductor
External
Interface
Signals