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msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:15
PPCM
16:31
DR
12.4.5.3
USB HC Rh Status Register—MBAR + 0x1050
This register is divided into two parts. The lower 16 bits of a 32-bit word represents the hub status field; the upper word represents the hub
status change field. Reserved bits should always be written 0.
msb 0
1
R
CRWE
W
RESET:
0
0
16
17
R
DRWE
W
RESET:
0
0
Freescale Semiconductor
Table 12-20. USB HC Rh Descriptor B Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
PortPowerControlMask—each bit indicates whether a port is affected by a global power
control command when PSM is set.
•
When set, port power state is only affected by per-port power control
(Set/ClearPortPower).
•
When cleared, port is controlled by the global power switch
(Set/ClearGlobalPower).
If device is configured to Global Switching Mode (PSM=0), this field is not valid.
bit 0—Reserved
bit 1—Ganged-power mask on Port #1
bit 2—Ganged-power mask on Port #2
...
bit15—Ganged-power mask on Port #15
NDeviceRemovable—each bit is dedicated to a Root Hub port. When cleared, the attached
device is removable. When set, the attached device is not removable.
bit 0—Reserved
bit 1—Device attached to Port #1
bit 2—Device attached to Port #2
...
bit15—Device attached to Port #15
Table 12-21. USB HC Rh Status Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
Host Control (HC) Operational Registers
7
8
9
10
PPCM
0
0
0
0
23
24
25
26
DR
0
0
0
0
Description
7
8
9
10
Reserved
0
0
0
0
23
24
25
26
Reserved
0
0
0
0
11
12
13
14
15
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
11
12
13
14
15
OCIC
LPSC
0
0
0
0
27
28
29
30
31 lsb
OCI
LPS
0
0
0
0
0
0
0
0
12-21
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