Psc2 Mclock Config Register—Mbar + 0X022C; Psc3 Mclock Config Register—Mbar + 0X - Freescale Semiconductor MPC5200B User Manual

CDM Registers
5.5.12 PSC2 Mclock Config Register—MBAR + 0x022C
This register controls the generation of the Mclock for PSC2. Before modify the register value the divider must be disabled.
msb 0 1
R
W
RESET: 0 0
16 17
R
W
RESET: 1 0
Bit Name
0–15 —
16 Mclock Enable
17-22 —
23-31 MclkDiv[8:0]
5.5.13 PSC3 Mclock Config Register—MBAR + 0x0230
This register controls the generation of the Mclock for PSC3. Before modify the register value the divider must be disabled.
16 17
R
W
RESET: 1 0
Bit Name
0–15 —
16 Mclock Enable
17-22 —
23-31 MclkDiv[8:0]
5-22
Table 5-19. CDM PSC2 Mclock Config
2 3 4 5
0 0 0 0
18 19 20 21 22
Reserved
Write 0
0 0 0 0
Reserved for future use. Write 0.
PSC2 Mclock enable.
bit=0:Turns off internally generated Mclock.
bit=1:Turns on internally generated Mclock.
Reserved for future use. Write 0.
The counter divide the f
register turns off internally generated Mclock.
For example, a value of 7 in this register, where fsystem clock is at a frequency of
528MHz would result in a Mclock rate of 528/8, or 66 MHz.
Note: f clock is always 12 or 16 times the reference clock, sys_xtal_in,
system
depending on sys_pll_cfg_0 at reset.
Table 5-20. CDM PSC3 Mclock Config
18 19 20 21 22
Reserved
Write 0
0 0 0 0
Reserved for future use. Write 0.
PSC3 Mclock enable.
bit=0:Turns off internally generated Mclock.
bit=1:Turns on internally generated Mclock.
Reserved for future use. Write 0.
The counter divide the f
register turns off internally generated Mclock.
For example, a value of 7 in this register, where fsystem clock is at a frequency of
528MHz would result in a Mclock rate of 528/8, or 66 MHz.
Note: f clock is always 12 or 16 times the reference clock, sys_xtal_in,
system
depending on sys_pll_cfg_0 at reset.
MPC5200B Users Guide, Rev. 1
6 7 8 9 10
Reserved
Write 0
0 — 0 0 0
23 24 25 26
0 0 0 0 0
Description
frequency by MclkDiv+1. A vallue of 0x00 in this
system
23 24 25 26
0 0 0 0 0
Description
frequency by MclkDiv+1. A vallue of 0x00 in this
system
11 12 13 14
0 0 0 0
27 28 29 30
MclkDiv[8:0]
0 1 1 1
27 28 29 30
MclkDiv[8:0]
0 1 1 1
Freescale Semiconductor
15
—
31 lsb
1
31 lsb
1