Arbiter Address Capture Register (Xarb_Adrcap); Arbiter Bus Signal Capture Register (Xarb_Sigcap) - Freescale Semiconductor MCF5480 Reference Manual

Bits Name
1 DTE
0 ATE

10.3.3.5 Arbiter Address Capture Register (XARB_ADRCAP)

The arbiter address capture register will capture the address for a tenure that has an address time-out, data
time-out, or there is a transfer error acknowledge from another source. This value is held until unlocked
by writing any value to the arbiter address capture register or arbiter bus signal capture register. This value
is also unlocked by writing a 1 to either XARB_SR[DT] or XARB_SR[AT]. Unlocking the register does
not clear its contents.
31 30 29
R
W
Reset 0 0
15 14 13
R
W
Reset 0 0
Reg
Addr
Figure 10-9. Arbiter Address Capture Register (XARB_ADRCAP)
Bits Name
31–0 ADRCAP

10.3.3.6 Arbiter Bus Signal Capture Register (XARB_SIGCAP)

Important bus signals are captured when a bus error occurs. This happens on an address time-out, data
time-out, or any transfer error acknowledge.
The arbiter bus signal capture register will capture TT, TBST, and TSIZ for a tenure that has an address
time-out or data time-out, or there is a transfer error acknowledge from another source. These values are
held until unlocked by writing any value to the arbiter address capture register (XARB_ADRCAP) or
arbiter bus signal capture register (XARB_SIGCAP). These values are also unlocked by writing a 1 to
either XARB_SR[DT] or XARB_SR[AT]. Unlocking the register does not clear its contents.
Freescale Semiconductor
Table 10-8. XARB_IMR Field Descriptions (Continued)
Data Tenure Time-out interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
Address Tenure Time-out interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
28 27 26
0 0 0 0
12 11 10
0 0 0 0
Table 10-9. XARB_ADRCAP Field Descriptions
Address that is captured when a bus error occurs. This happens on an address time-out,
data time-out, or any transfer error acknowledge.
MCF548x Reference Manual, Rev. 3
Description
25 24 23 22
ADRCAP
0 0 0 0
9 8 7 6
ADRCAP
0 0 0 0
MBAR + 0x0250
Description
21 20 19 18
0 0 0 0
5 4 3 2
0 0 0 0
XL Bus Arbiter
17 16
0 0
1 0
0 0
10-13