Gpt 0 Status Register—Mbar + 0X060C - Freescale Semiconductor MPC5200B User Manual

Freescale semiconductor board users guide
Table of Contents

Advertisement

Bit
Name
23
PWMOP
Pulse Width Mode Output Polarity—Defines PWM output polarity for OFF time. Opposite state is
ON time polarity. PWM cycles begin with ON time.
24:30
Reserved
31
LOAD
Bit forces immediate period update. Bit auto clears itself. A new period begins immediately with
the current count and width settings.
If LOAD = 0, new count or width settings are not updated until end of current period.
Note: Prescale setting is not part of this process. Changing prescale value while PWM is active
causes unpredictable results for the period in which it was changed. The same is true for
PWMOP bit.
7.4.4.4
GPT 0 Status Register—MBAR + 0x060C
GPT 1 Status Register—MBAR + 0x061C
GPT 2 Status Register—MBAR + 0x062C
GPT 3 Status Register—MBAR + 0x063C
GPT 4 Status Register—MBAR + 0x064C
GPT 5 Status Register—MBAR + 0x065C
GPT 6 Status Register—MBAR + 0x066C
GPT 7 Status Register—MBAR + 0x067C
This is a read-only register.
msb 0
1
R
W
RESET:
0
0
16
17
R
Rsvd
W
RESET:
0
0
Bit
Name
0:15
Capture
Read of internal counter, latch at reference event. This is pertinent only in IC mode, in which case
it represents the count value at the time the Input Event occurred. Capture status does not
shadow the internal counter while an event is pending, it is updated only at the time the Input
Event occurs.
Note: If ICT is set to 11, which is Pulse Capture Mode, the Capture value records the width of
the pulse. Also, the Stop_Cont bit is irrelevant in Pulse Capture Mode, operation is as if
Stop_Cont were 0.
16
Reserved
Freescale Semiconductor
Table 7-50. GPT 0 Status Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
OVF
Reserved
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
Description
GPT 1 Status Register
GPT 2 Status Register
GPT 3 Status Register
GPT 4 Status Register
GPT 5 Status Register
GPT 6 Status Register
GPT 7 Status Register
7
8
9
10
CAPTURE
0
0
0
0
23
24
25
26
PIN
Reserved
0
0
0
0
Description
General Purpose Timers (GPT)
11
12
13
14
0
0
0
0
27
28
29
30
TEXP PWMP COMP CAFT
0
0
0
0
15
0
31 lsb
0
7-61

Advertisement

Table of Contents
loading

Table of Contents