Freescale Semiconductor MPC5200B User Manual page 632

2
18.3.4 I C Status Register (MSR)—MBAR + 0x3D0C / 0x3D4C
msb 0 1
R CF AAS
W
RESET: 0 0
16 17
R
W
RESET: 0 0
Bit Name
0 CF Data transferring—bit clears while 1Byte of data is being transferred. Bit is set by falling edge of
9th clock of a byte transfer.
1 AAS Addressed As Slave—bit sets when its own specific address (I
with the calling address. The CPU is interrupted provided IEN is set. The CPU then needs to check
the SRW bit and set its Tx/Rx mode accordingly. Writing to the I
2 BB Bus Busy—bit indicates bus status. When a START signal is detected, BB is set. If a STOP signal
is detected, it is cleared.
3 AL Arbitration Lost—bit is set by hardware when the arbitration procedure is lost. Arbitration is lost in
the following circumstances:
1. SDA sampled low when master drives high during an address or data Tx cycle.
2. SDA sampled low when master drives high during a data Rx cycle acknowledge bit.
3. Start cycle is attempted when bus is busy.
4. A repeated start cycle is requested in slave mode.
5. Stop condition is detected when not requested by master. Software must clear bit
4 AKF Acknowledge Cycle Falling Edge when Arbitration Lost AND Addressed as Slave - bit
is set by hardware upon the falling edge of the acknowledge cycle after arbitration has
been lost and addressed as slave. In this very specific case, the interrupt (IF=1) is
really the 2nd one set by the hardware (which is a side-effect of a fix to make the I2C
module fully I2C-spec compliant - see note in section 18.5.3 Special note on AKF), The
software must use this bit to distinguish if the interrupt is the first one (set upon rising
edge of acknowledge cycle) or the second one (set upon falling edge of acknowledge
cycle). The software should only take action for AL & AAS if the interrupt is the second
one, the "traditional time" for the interrupt.
0 = 1st interrupt on rising edge of acknowledge cycle- software should not take AL&AAS ac-
tion (see later section for typical software flow diagram).
1 = 2nd interrupt on falling edge of acknowledge - software should take AL&AAS action
This bit must be cleared by software writing it low in the interrupt routine
Freescale Semiconductor
Table 18-6. I
2 3 4 5 6
BB AL AKF SRW IF
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
0 = Transfer in progress
1 = Transfer complete
0 = Not addressed
1 = Addressed as a slave
0 = Bus is idle
1 = Bus is busy
by writing it low.
MPC5200B Users Guide, Rev. 1
2
C Status Register
7 8 9 10
RXAK
0 0 0 0
23 24 25 26
Reserved
0 0 0 0
Description
2
I C Interface Registers
11 12 13 14
Reserved
0 0 0 0
27 28 29 30 31 lsb
0 0 0 0
2
C Address Register) is matched
2
C Control Register clears this bit.
15
0
0
18-15