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Programmable Serial Controller (PSC)
Table 15-92. Configuration Sequence Example for MIR Mode
Register
IMR
Port_Config
CR
15.3.4.3
PSC in FIR Mode
The FIR mode is also a supported IrDA mode. This section will give some more informations about this mode. The important registers to
configure the PSC6 (only this PSC support the IrDA modes) for FIR mode are:
•
SICR
register - select the FIR mode
•
MR2
register - Channel Mode
•
If clock generate from the internal source:
— cdm_irda_bitclk_config - select Mclk frequency, see
— cdm_clock_enable_register - enable Mclk, see
— CCR- select BitClk and Frame Frequency
•
IRCR1
register - full duplex and SIP mode
•
IRMDR register - select the clock divider
•
RFALARM,
TFALARM
•
CR
register - enable or disable receiver and transmitter
•
Port_config - select the right Pin-Muxing, see
15.3.4.3.1
Block Diagram and Signal Definition for FIR Mode
The signal definition for FIR mode is the same as in SIR mode. Please see
The clock generation is the same as in MIR mode, see
15.3.4.3.2
Transmitting and Receiving in FIR Mode
The data field is 4PPM encoded by the transmitter. Data encoding is done LSB first. Each chip duration is 125 ns.
0
binary data
4PPM data
The packet format is defined as
PA
The preamble (PA) field is used by a receiver to establish phase lock. After receiving the start flag (STA), the receiver begin to interpret the
4PPM encoded symbols. The receiver continues receiving until it receives the stop flag (STO). Like the UART mode, the FIR mode sends the
lsb first. For more informations regarding the pulse width and Baud rate calculations see
(0x54)—IRFDR.
The FCS is 32 bit CRC defined as:
CRC x ( )
15-70
Value
0xXXXX
0x00F00000
0x05
Section 5.5.6, CDM Clock Enable Register—MBAR + 0x0214
- select the FIFO "Alarm" level
Chapter 2, Signal Descriptions
Section 15.3.4.2.1, Block Diagram and Signal Definition for MIR Mode.
0
0
1
1
0
1
1
Figure 15-21. Data Format in FIR Mode
STA
32
26
23
22
=
x
+
x
+
x
+
x
+
x
MPC5200B Users Guide, Rev. 1
Notes
select the desired interrupt
Select the Pin-Muxing for IrDA mode, see
Descriptions
Enable Tx and Rx
Section 5.5.14, PSC6 (IrDA) Mclock Config Register—MBAR + 0x0234
Table
15-90.
Figure 15-19.
bit pair 4PPM data
00
01
10
11
DATA
FCS
Section 15.2.27, Infrared FIR Divide Register
10
16
12
11
8
7
+
x
+
x
+
x
+
x
+
x
+
Setting
Chapter 2, Signal
shows the Block diagram for FIR mode.
1000
0100
0010
0001
STO
5
4
2
x
+
x
+
x
+ +
x
1
Freescale Semiconductor
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