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Bits
Name
0:31
FIFO_Data_Word
9.7.3.2
LPC Rx/Tx FIFO Status Register—MBAR + 0x3C44
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:8
—
9
Err
10
UF
11
OF
12
Full
13
HI
14
LO
15
Emty
16:31
—
Freescale Semiconductor
The FIFO data port. Reading from this location "pops" data from the FIFO, writing
"pushes" data into the FIFO. During normal operation the BestComm Controller
pushes data here.
Note: ONLY full word access is allowed. If all byte enables are not asserted when
accessing this location, a FIFO error flag is generated.
Table 9-19. LPC Rx/Tx FIFO Status Register
2
3
4
5
6
Reserved
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Reserved
Error—flag bit is essentially the logical "OR" of other flag bits and can be polled for detection
of any FIFO error. After clearing the offending condition, writing 1 to this bit clears flag.
UnderFlow—flag indicates read pointer has surpassed the write pointer. FIFO was read
beyond empty. Resetting FIFO clears this condition; writing 1 to this bit clears flag.
OverFlow—flag indicates write pointer surpassed read pointer. FIFO was written beyond full.
Resetting FIFO clears this condition; writing 1 to this bit clears flag.
FIFO full—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
High—FIFO requests attention, because high level alarm is asserted. To clear this condition,
FIFO must be read to a level below the setting in granularity bits.
Low—FIFO requests attention, because Low level alarm is asserted. To clear this condition,
FIFO must be written to a level in which the space remaining is less than the granularity bit
setting.
FIFO empty—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
Reserved
MPC5200B Users Guide, Rev. 1
Description
7
8
9
10
11
Err
UF
OF
0
0
0
0
23
24
25
26
27
Reserved
0
0
0
0
Description
Programmer's Model
12
13
14
15
Full
HI
LO
Emty
0
0
0
1
1
28
29
30
31 lsb
0
0
0
0
0
9-29
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