Lpc Concept Diagram - Freescale Semiconductor MPC5200B User Manual

9.3.2 Block Diagram
The block diagram of the LocalPlus Controller (LPC) is shown in
address and data lines.
The LPC is driven by the internal IP bus clock and the PCI_CLOCK. The supported ratios of the IP bus clock to the reference clock
PCI_CLOCK (the one externally seen by peripherals) are 4:1, 2:1 and 1:1.
The reference clock is the PCI_CLOCK and all clock counts are referred to this clock. All transitions are synchronized to the rising edge of
the PCI_CLOCK.
Start/Stop registers to define the CS address range for each CS output are contained in the MPC5200B MMAP register group, see
Section 3.3.3.2, Boot and Chip Select
Internal Register Map. For more information, see
and peripheral, when a "hit" occurs in the MMAP module for the corresponding CS space.
XL Bus
IPBI
MMAP
PCI Arbiter
CDM
For multiplexed bus implementation, external logic is required to capture the address phase as shown in
Freescale Semiconductor
Addresses. Registers in the LPC are accessed through the address range specified in the MPC5200B
Section 9.7, Programmer's
IP bus Data
Registers
Shared Data
8 cs "hit"
ext_add
32
AD bus Request
AD bus Grant
IPB_CLK
Figure 9-1. LPC Concept Diagram
BestComm Interface + FiFo not shown
Not all pins are used in all modes.
MPC5200B Users Guide, Rev. 1
Figure 9-1. This diagram shows the non-multiplexed implementation of
Model. These registers control the operation of a particular CS
Variable Width
Address
Variable Width
R/W Data
R/W
ACK
LPC
ALE
TS
OE
TSIZ[1:2]
2
CS[0:7]
8
PCI_CLOCK
NOTE
Interface
AD[31:0]
multiplexed
with PCI, ATA
Figure 9-2.
9-3