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The PCI Arbiter implements a Round-Robin fairness algorithm, which avoids the domination of the bus by high-priority masters and
exclusion of low-priority masters. The PCI Arbiter is capable of Parking the current Master to stay on last master in absence of other requests.
The support of the non-PCI clients presents special challenges to the arbitration scheme.
The PCI Arbiter runs independently. The programmability consists of a Soft Reset, which allows to reset the PCI Arbiter, and one status bit
to detect the Broken Master condition. and a corresponding enable bit for the generation of a CPU interrupt for the Broken Master condition.
All these register bits are located in registers of the PCI Controller.
In case of broken master detection the external PCI REQ# will be dis-connected internally and will be re-connected after external deassertion
of PCI REQ# or by software (Softreset) or by Hardreset. After broken master detection (bus idle for 16 clocks) the arbiter will ignore any PCI
FRAME# assertion.
The PCI Arbiter does not support preemption of the internal masters XIPCI or SCPCI. The internal master is granted until the transaction has
been completed. The Latency Timer (LT) cannot terminate any transfer.
10.6
Application Information
This section provides example usage of some of the features of the PCI module.
10.6.1
XL bus Initiated Transaction Mapping
The use of the PCI Configuration Address Register along with the initiator window registers provide many possibilities for PCI command and
address generation.
Table 10-15
different address ranges resulting in the generation of memory, I/O, configuration, interrupt acknowledge and special cycles on the PCI bus.
The Window Registers are defined in
0x0D74
through
Section 10.3.2.8, Initiator Window Configuration Register PCIIWCR(RW) —MBAR +
XL bus Transaction
(XL Bus Slave Interface)
Single-Beat 1 -> 8 byte Read
Burst Read (32 bytes)
Single-Beat 1 -> 8 byte Read
Burst Read
Burst Read
Single-Beat 1 -> 8 byte Read
Burst Read
Single-Beat 1 -> 8 byte, or Burst
Write
Single-Beat 1 -> 4 byte Read
Single-Beat 1 -> 4 byte Write
Single-Beat 1 -> 4 byte Read
Single-Beat 1 -> 4 byte Write
Single-Beat 1 -> 4 byte Read
Freescale Semiconductor
shows how the PCI Controller accepts read and write requests from a XLB bus master and decodes them to
Section 10.3.2.6, Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW) —MBAR +
Table 10-15. Transaction Mapping: XL Bus -> PCI
Cache Line
Configuration bits
Size
Register=
8
x
x
x
false
true
x
x
x
x
x
x
x
x
MPC5200B Users Guide, Rev. 1
Initiator Register Settings
Configuration
Initiator Window
Address
Register
IO/M#
PRC
En
0
b00
x
0
b00
x
0
b01
x
0
b01
x
0
b01
x
0
b10
x
0
b10
x
0
x
x
1
x
0
1
x
0
1
x
1
1
x
1
1
x
1
Application Information
0x0D80.
PCI Transaction
Controller (XL Bus
Initiator Interface) ->
device
PCI Target
number
==
b1_1111
x
Memory Read
x
Memory Read
x
Memory Read
x
Memory Read
x
Memory Read Line
x
Memory Read Multiple
x
Memory Read Multiple
x
Memory Write
x
I/O Read
x
I/O Write
false
Configuration Read
false
Configuration Write
true
Interrupt acknowledge
10-63
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