Freescale Semiconductor MPC5200B User Manual page 546

Table 15-49. Infrared SIR Divide Register (0x48) for SIR Mode
msb 0
R
W
RESET: 0
Table 15-50. Infrared SIR Divide Register (0x48) for other Modes
msb 0
R
W
RESET: 0
Bit Name
0:7 IRSTIM
15.2.26 Infrared MIR Divide Register (0x50)—IRMDR
This register set the MIR mode Baud rate. This register is reserved in other modes.
Table 15-51. Infrared MIR Divide Register (0x50) for MIR Mode
msb 0
R FREQ
W
RESET: 0
Table 15-52. Infrared MIR Divide Register (0x50) for other Modes
msb 0
R
W
RESET 0
:
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
1 2
0 1
1 2
0 0
SIR—Timer counter value for 1.6us pulse
In SIR mode, this is used to make 1.6 µs pulse when SPUL in the
should be set so that
IPB clock period * IRSTIM = 1.6 µs
Reset value is 54(0x36) and this is for 33 MHz bus clock.
other Modes—Reserved
1 2
0 0
1 2
0 0
MPC5200B Users Guide, Rev. 1
3 4 5
IRSTIM[0:7]
1 0 1
3 4 5
Reserved
0 0 0
Description
3 4 5
M_FDIV
0 0 0
3 4 5
Reserved
0 0 0
6 7 lsb
1 0
6 7 lsb
0 0
IRCR1 is high. This value
6 7 lsb
0 0
6 7 lsb
0
15-35