Base Address Register Overview; Outbound Address Map - Freescale Semiconductor MPC5200B User Manual

Application Information
MPC5200B Space
0
MBAR
Register Space
1G
Window 0
XL Bus Initiator
Windows
Window 1
2G
Window 2
3G
4G
Associated with PCI Prefetchable Memory
Associated with PCI I/O
Associated with PCI Non-Prefetchable Memory
10.6.2.1.3

Base Address Register Overview

Table 10-15 shows the available accessibility for all PCI associated base address and translation address registers in MPC5200B.
Base Address
Register
BAR0 PCI Base Address Register 0
(256 Kbyte)
BAR1 PCI Base Address Register 1 (1
Gbyte)
TBATR0 Target Base Address
Translation Register 0
(256Kbyte)
TBATR1 Target Base Address
Translation Register 0 (1 Gbyte)
IMWBAR Initiator Window
Base/Translation Address
Registers
10-66
PCI Space (Memory View)
0
Window 0
1G
Translation
Not Recommended
Window 1
Translation
2G
Not Recommended
Window 2
Translation
3G
4G
Window 0 Base Address = 0x40
Window 0 Address Mask = 0x1F
Window 0 Translation Address = 0x00
Window 1 Base Address = 0x70
Window 1 Address Mask = 0x0F
Window 1 Translation Address = 0x70
Figure 10-9. Outbound Address Map
Register Function
MPC5200B Users Guide, Rev. 1
PCI Space (IO View)
0
Window 0
1G
MPC5200
B mem-
Window 1
2G
MPC5200B mem-
3G
Window 2
4G
PCI Bus Configuration Processor
Access
X
X
PCI Space (Configuration View)
0
1G
2G
3G
4G
Window 2 Base Address = 0x80
Window 2 Address Mask = 0x3F
Window 2 Translation Address = 0xC0
Any XL bus Master
Access Access
X X
X X
X X
X X
X X
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