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Freescale Semiconductor
Application Note
PowerQUICC III MPC8555E and
MPC8541E Bring-Up Guidelines
by
Freescale Semiconductor, Inc.
This document provides bring-up guidelines for designs
based on the MPC8555E and the MPC8541E devices from
the PowerQUICC III family of integrated communications
processors (collectively referred to throughout this
document as PowerQUICC III). This document can also be
useful in debugging newly designed systems by highlighting
the aspects of a design that merit special attention during
initial system startup.
1
Getting Started
This section outlines recommendations to simplify the first
phase of design. Before designing a system with a
PowerQUICC III device, it is recommended that you
familiarize yourself with the available documentation,
software, microcodes, models, and tools.
© 2013 Freescale Semiconductor, Inc. All rights reserved.
Document Number: AN2805
Rev. 5, 05/2013
Contents
1. Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. Power-On Reset/Reset Configurations . . . . . . . . . . . 13
6. Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Related Manuals for Freescale Semiconductor PowerQUICC III MPC8555E
Summary of Contents for Freescale Semiconductor PowerQUICC III MPC8555E
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Page 1: Table Of Contents
This section outlines recommendations to simplify the first phase of design. Before designing a system with a PowerQUICC III device, it is recommended that you familiarize yourself with the available documentation, software, microcodes, models, and tools. © 2013 Freescale Semiconductor, Inc. All rights reserved. - Page 2 The boot sequencer tool is a C code file. When compiled and given a sample data file, it generates the appropriate raw data format as outlined in the MPC8555ERM—that is, an s-record file that can be used to program the EEPROM. PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
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Page 3: Power
This increases the complexity of the system because multiple voltage supplies and PCB power planes are required for the design. No external signals on PowerQUICC PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor... - Page 4 To guarantee MCKE low during power-up, GVDD should be the last power supply to come up. If there is no concern about any of the DDR signals being in an indeterminate state during power-up, then the sequencing is not required. PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
- Page 5 Suggested bulk capacitors—100–330 µF. Simulation is strongly recommended to minimize noise on the power supplies before proceeding into the PCB design and manufacturing stage of development. PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
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Page 6: Clocking
PCI clock input unrelated to the SYSCLK input. The PCI clock modes are configured during POR by TSEC2_TXD1, and TSEC2_TXD0 signals. See Figure 2 Table PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor... - Page 7 Table 3. Clocking Quick Reference Functional Block Clock Derivation Core (including L1) CCB [2, 2.5, 3, 3.5] CCB / 2 CCB / (I2CFDR ratio) L2 cache, CPM Local Bus CCB / [2,4,8] PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
- Page 8 The DDR SDRAM clock outputs MCK[0:5] and MCK[0:5] are derived from the CCB clock. No configuration pins or register settings are required to generate the MCK/MCKn frequencies because they are by default one-half the CCB clock frequency. PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
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Page 9: Debug
TBI mode, EC_GTX_CLK125 is a 125 MHz input into the TSEC and is used to generate all 125-MHz-related signals and clocks. Debug This section describes the PowerQUICC III reset sequence and recommendations for the system. PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor... - Page 10 HRESET to reset all logic completely on the PowerQUICC III. For compatibility with third-party tools, TRST and HRESET must be able to assert independently (see the example in Figure PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
- Page 11 TRST line. If BSDL testing is not being performed, this switch should be closed or removed. 6. Asserting SRESET causes a machine check interrupt to the e500 core. Figure 3. COP Connections to PowerQUICC III PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
- Page 12 TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
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Page 13: Power-On Reset/Reset Configurations
The core is allowed to boot without waiting for configuration from any external master Boot Sequencer LGPL3, LGPL5 Boot sequencer is disabled TSEC Width EC_MDC Ethernet interfaces operate in standard GMII or TBI modes PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor... - Page 14 For example, we can pass information about a circuit board revision number to software by driving the pins in any order. The information is automatically sampled from LAD[0:31] during POR. Then software PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
- Page 15 C pins continue to be pulled low during a fail until a hard reset occurs. The CRC algorithm used by the boot sequencer is as follows: 1 + x PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
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Page 16: Functional Blocks
DEVDISR. However, because you cannot wake up the device using DEVDISR, except through an HRESET, it is recommended that nap mode be used instead. PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor... - Page 17 For proper operation, the external signals MSYNC_IN and MSYNC_OUT should be connected to each other. • The source synchronous mode bit field must be set during initilization: DDR_SDRAM_CLK_CNTL[SS_EN] = 1 PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
- Page 18 DDR. The PowerQUICC III local bus features a multiplexed address and data bus, LAD[0:31]. An external latch is required to de-multiplex these signals to the connecting device. PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
- Page 19 TSEC2_TXD[6:5]. These pins directly affect local bus AC-timing by adding up to three buffer delays to the output path. The default configuration is a single buffer delay. Fewer buffer delays are needed in cases where the connection is to a faster external device. PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
- Page 20 If the PowerQUICC III is the host that initiates PCI transactions, you should pull the IDSEL pin low to guard against the PowerQUICC III replying to one of its own bus transactions. PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
- Page 21 DMACTL[GTS] bit and confirming that it has completed by polling the IEVENT [GTSC] bit. Only then should the transmitter be disabled by clearing the MACCFG1[TxEN] bit. PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
- Page 22 Tie inputs to inactive state through resistor manufacturing test pins TSEC1_TXD[0:3] Tie I/Os high or low through resistor POR pins LA[27:31], LALE, LGPL[0:3], LGPL5, LWE[0:3] Local Bus Tie inputs to inactive state through resistor PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5 Freescale Semiconductor...
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Page 23: Revision History
Revision History Table 11 provides a revision history for this application note. Table 11. Document Revision History Rev. Date Changes Number “..minimum of 100ms” to “..minimum of 100μs” in Section 5, 05/2013 Changed “Power-On Reset/Reset Configurations 06/2010 Added a NOTE to Section 2.3, “Power Sequencing.”... - Page 24 Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. CoreNet, Layerscape, QorIQ Qonverge, QUICC Engine, Tower, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks...
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