Freescale Semiconductor MPC5200B User Manual page 740

Appendix A
Acronyms and Terms
This section contains an alphabetical list of terms, phrases, acronyms, and abbreviations used in this book. Some terms and definitions
included are reprinted from IEEE Std. 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, copyright ©1985 by the Institute of
Electrical and Electronics Engineers, Inc. with permission of the IEEE.
A
AAL . . . . . . . . . . . . . . . . . . . ATM Adaptation Layer
ABR . . . . . . . . . . . . . . . . . . . Available Bit-Rate. See also CBR and UBR.
ACR . . . . . . . . . . . . . . . . . . . Allowed Cell Rate
addr, adr . . . . . . . . . . . . . . . . address
alm . . . . . . . . . . . . . . . . . . . . alarm
ALE. . . . . . . . . . . . . . . . . . . . Address Latch Enable
ALU . . . . . . . . . . . . . . . . . . . Arithmetic Logic Unit
APC. . . . . . . . . . . . . . . . . . . . ATM Pace Control unit
ARB . . . . . . . . . . . . . . . . . . . Microprocessor Arbitor
Architecture . . . . . . . . . . . . . A detailed specification of requirements for a processor or computer system. It does not specify details of how
the processor or computer system must be implemented; instead it provides a template for a family of
compatible implementations.
Asynchronous exception. . . . Exceptions that are caused by events external to the processor's execution. In this document, the term
'asynchronous exception' is used interchangeably with the word interrupt.
AT . . . . . . . . . . . . . . . . . . . . . Address Types
ATA . . . . . . . . . . . . . . . . . . . . Advanced Technology Attachment—a standard interface used with storage devices such as hard disk drives.
ATA drives are also referred to as Integrated Drive Electronics (IDE) drives.
ATAPI . . . . . . . . . . . . . . . . . . ATA Packet Interface
ATM . . . . . . . . . . . . . . . . . . . Asynchronous Transfer Mode
Atomic access . . . . . . . . . . . . A bus access that attempts to be part of a read-write operation to the same address uninterrupted by any other
access to that address (the term refers to the fact that the transactions are indivisible). The PowerPC architecture
implements atomic access through the lwarx/stwcx instruction pair.
Autobaud. . . . . . . . . . . . . . . . The process of determining a serial data rate by timing the width of a single bit.
B
BAT . . . . . . . . . . . . . . . . . . . . Block Address Translation
BB . . . . . . . . . . . . . . . . . . . . . Bus Busy
BD. . . . . . . . . . . . . . . . . . . . . Buffer Descriptor
BG. . . . . . . . . . . . . . . . . . . . . Bus Grant
BI . . . . . . . . . . . . . . . . . . . . . Burst Inhibit
Big-Endian (BE). . . . . . . . . . A byte-ordering method in memory where the address n of a word corresponds to the Most-Significant Byte. In
an addressed memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the Most-Significant
Byte. See also Little-Endian.
. . . . . . . . . . . . . . . . . . . . . . . In Big-Endian architectures, the leftmost bytes (those with a lower address) are most significant. For example,
consider the number 1025 stored in a 4Byte integer as shown in the table below.
Addr
00
01
02
03
Freescale Semiconductor
00000000 00000000 00000100 00000001
Big-Endian
00000000
00000000
00000100
00000001
MPC5200B Users Guide, Rev. 1
Little-Endian
00000001
00000100
00000000
00000000
A
A-1