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7.3.2.1.5
GPS Simple GPIO Data Output Values Register —MBAR + 0x0B10
msb 0
1
R
Reserved
W
RESET:
0
0
16
17
R
Reserved
W
RESET:
0
0
Bit
Name
0:1
—
2:3
IRDA
4:7
ETHR
8:11
—
12:15
USB
16:17
—
18:23
PSC3
Freescale Semiconductor
Table 7-25. GPS Simple GPIO Data Output Values Register
2
3
4
5
6
IRDA
ETHR
0
0
0
0
0
18
19
20
21
22
PSC3
0
0
0
0
0
Reserved
Individual bits to control the state of pins configured as GPIO output.
bit 2 controls GPIO_IRDA_1 (IR_USB_CLK pin)
bit 3 controls GPIO_IRDA_0 (IRDA_TX pin)
0 = Drive 0 on the pin (default)
1 = Drive 1 on the pin
Individual bits to control the state of pins configured as GPIO output.
bit 4 controls GPIO_ETHI_3 (ETH_11 pin)
bit 5 controls GPIO_ETHI_2 (ETH_10 pin)
bit 6 controls GPIO_ETHI_1 (ETH_9 pin)
bit 7 controls GPIO_ETHI_0 (ETH_8 pin)
0 = Drive 0 on the pin (default)
1 = Drive 1 on the pin
Reserved
Individual bits to control the state of pins configured as GPIO output.
bit 12 controls GPIO_USB_3 (USB1_8 pin)
bit 13 controls GPIO_USB_2 (USB1_7 pin)
bit 14 controls GPIO_USB_1 (USB1_6 pin)
bit 15 controls GPIO_USB_0 (USB1_0 pin)
0 = Drive 0 on the pin (default)
1 = Drive 1 on the pin
Reserved
Individual bits to control the state of pins configured as GPIO output.
bit 18 controls GPIO_ PSC3_5 (PSC3_7 pin)
bit 19 controls GPIO_ PSC3_4 (PSC3_6 pin)
bit 20 controls GPIO_ PSC3_3 (PSC3_3 pin)
bit 21 controls GPIO_ PSC3_2 (PSC3_2 pin)
bit 22 controls GPIO_ PSC3_1 (PSC3_1 pin)
bit 23 controls GPIO_ PSC3_0 (PSC3_0 pin)
0 = Drive 0 on the pin (default)
1 = Drive 1 on the pin
MPC5200B Users Guide, Rev. 1
7
8
9
10
11
Reserved
0
0
0
0
23
24
25
26
27
PSC2
0
0
0
0
Description
General Purpose I/O (GPIO)
12
13
14
15
USB
0
0
0
0
0
28
29
30
31 lsb
PSC1
0
0
0
0
0
7-37
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