Freescale Semiconductor MPC5200B User Manual page 523

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
15.2.4 Clock Select Register (0x04)
The MPC5200B supports only the internal clock as source for the UART / SIR clock generation. For the UART clock generation a prescaler
by 32 or 4 is available. For the SIR clock generation only the prescaler by 32 is valid. After reset, the prescaler by 4 for the UART mode and
the prescaler by 32 for the SIR mode is selected. Writing "1110" to this register will stop the UART / SIR clock generation.
Table 15-14. Clock Select Register (0x04) for UART / SIR Mode
msb 0 1
R
W RCS
RESET: 0 0
msb 0 1
R
W
RESET: 0 0
Bit Name
0:3 RCS
4:7 TCS
8:15 —
15.2.5 Command Register (0x08)
The write-only command registers (CR), provide the commands to the PSC in all modes. Only multiple commands that do not conflict can be
specified in a single write to a CR. For example, reset Tx and enable Tx cannot be specified in one command.
15-12
—
2 3 4 5 6
TCS
0 0 0 0 0
Table 15-15. Clock Select Register (0x04) for other Modes
2 3 4 5 6
0 0 0 0 0
UART—Receiver Clock Select Register
0000 -1101 = choose the prescaler by 32 for the UART receive clock generation
1110 = disable the clock generation
1111 = choose the prescaler by 4 for the UART receive clock generation
SIR —Clock Select Register
1110 = disable the clock generation
others = choose the prescaler by 32 for the SIR receive clock generation
other Modes—Reserved
UART—Transmitter Clock Select Register
0000 -1101 = choose the prescaler by 32 for the UART transmit clock generation
1110 = disable the clock generation
1111 = choose the prescaler by 4 for the UART transmit clock generation
SIR —Clock Select Register
1110 = disable the clock generation
others = choose the prescaler by 32 for the SIR transmit clock generation
other Modes—Reserved
Reserved
CR
—
MPC5200B Users Guide, Rev. 1
CSR
7 8 9 10
0 0 0 0
7 8 9 10
Reserved
0 0 0 0
Description
11 12 13 14 15 lsb
Reserved
0 0 0 0
11 12 13 14 15 lsb
0 0 0 0
Freescale Semiconductor
0
0